Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Stretch | Subject: S6000 family
Edited by the Electronicstalk Editorial
Team on 12 March 2007
Configurable processor claims top
computing power
Software configurable processor architecture promises unprecedented single-chip computing power and the ability to easily scale to multichip implementations.
Stretch has announced its S6 software configurable processor (SCP) architecture Optimised specifically for high-performance video and wireless signal processing, the S6 Architecture offers unmatched price/performance in these demanding applications
This article was originally published on Electronicstalk on 4 Jul 2007 at 8.00am (UK)
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At the heart of the new architecture are three technology innovations: the second-generation Instruction Set Extension Fabric (ISEF), the processor array and the programmable accelerator.
The combination of these advancements provides unprecedented single-chip computing power and the ability to easily scale to multichip implementations for the most computing-intensive applications.
Commenting on the announcement, Craig Lytle, President and CEO said: "We are very excited about the new S6 architecture".
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"The S6000 family of devices will revolutionise the way in which people think of high performance signal processing solutions".
"Building on our experience with our groundbreaking S5 family of devices, and working very closely with our customers, we created a new architecture that delivers a price/performance point second to none in the industry".
The S6 architecture enables previously unattainable, single-chip implementations of applications such as H.264 high definition encoding.
A single S6000 family device can perform four channels of 4CIF/D1 H.264 BP encoding at 30frame/s or 16 channels of CIF resolution at 30frame/s, enabling H.264 encoding at less than US $1.60 per channel.
The S6 SCP Engine has Stretch's second generation Instruction Set Extension Fabric (ISEF) embedded directly within the Tensilica Xtensa LX dual-issue VLIW processor architecture.
The ISEF is a software configurable compute fabric that enables system designers to extend the processor instruction set and to define new instructions using C/C++ code.
These "extension instructions" are then automatically synthesised, placed, and routed into the ISEF.
Stretch has made several key improvements to the ISEF for the S6 architecture family, resulting in improved performance and reduced die area.
In addition to enhancements to the compute elements in the ISEF, 64Kbyte of distributed ISEF RAM (IRAM) has been added to allow for the storage of data within the ISEF itself.
To support the enhanced processing capabilities of the architecture, a dedicated high speed DMA channel has been added to ensure that data is always available.
Optimisation of the ISEF compute elements and routing structures provide 300MHz operation, three times the performance of the original architecture.
The new ISEF fabric can be dynamically reconfigured in less than thirty micro seconds, four times faster than the original fabric.
By using the Xtensa LX dual-issue VLIW architecture, the Stretch compiler technology may now pack multiple instructions in a single issuance, enabling up to twice the performance of the previous processor architecture.
"We have dramatically increased the performance of the S6 SCP engine through technology innovations, improved data transfer, and the usage of VLIW technology", stated Dr Albert Wang, Stretch Founder and CTO.
The increasing complexity and diversity of video and wireless standards are driving companies to create scalable systems with varying degrees of processing power, depending on the application requirements.
To enable its customers to easily create systems of varying compute levels, Stretch developed the processor array solution.
At the physical layer, each S6 device can interface with up to 4 other processors through dedicated 1.2Gbyte/s DDR interface banks, allowing system architects to create processor topologies best suited for their application.
So that the processor is not burdened with processor array functions, each S6 device has a dedicated processor network interface and switch circuitry to accommodate interprocessor communication.
At the software layer, programmers can dedicate tasks, establish communication channels between processors, and even share resources between processors using a rich library of BIOS calls or custom-created C/C++ code.
"The processor array enables customers to use a single processor architecture and easily scale from multichannel, SD resolution encoding or wireless CPE applications up to the most demanding High-Definition broadcast encoding/transcoding or wireless basestation applications", added Dr Wang.
Stretch accelerates common bottlenecks in video and wireless processing through a software-programmable accelerator, dramatically improving the performance of four computing-intensive functions: supporting CABAC for H.264 main profile encoding and CAVLC for H.264 baseline profile; accelerating sum-of-absolute-differences (SAD) calculations up to 64 billion SADs per second for motion estimation in algorithms such as H.264 and MPEG4; accelerating commonly used encryption protocols, such as AES and 3DES; and using the Tensilica Xtensa HiFi-2 Audio Engine to offer over 19 different audio codecs.
All programmable accelerator functions are accessed through a library of optimised object-code calls, enabling customers to quickly develop high-performance video and wireless processing designs.
"Through our customer engagements, we saw several opportunities to develop custom circuitry to accelerate common functions in video and wireless applications".
"Rather than create custom RTL blocks, we used a programmable approach that increases the flexibility and number of functions that can be accelerated using the same silicon real estate", said Lytle.
The S6000 family of devices has a rich set of I/O connectivity for seamless integration with system elements for the most demanding signal processing applications.
The S6000 devices are supported by the Stretch integrated development environment, which includes a code editor, an optimising compiler, and an instruction set simulator.
Also available is a comprehensive library of optimised code supporting DSP functions, wireless signal processing functions, and complete H.264 and MJPEG encoders and decoders.
The first member of the S6000 family, the S6105, will be available in the third quarter of 2007.
50,000-unit pricing for the S6105 is US $25 in 2008.
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