Product category:
Memory Devices and Modules
News Release from: STMicroelectronics | Subject: M50FLW080
Edited by the Electronicstalk Editorial
Team on 27 August 2004
Flash memory optimised for PC BIOS
storage
A new 8Mbit Flash memory provides storage of BIOS code in PCs based on both Intel and non-Intel chipsets, across a range of desktop computers, laptops and servers.
A new 8Mbit Flash memory provides storage of BIOS code in PCs based on both Intel and non-Intel chipsets, across a range of desktop computers, laptops and servers The chip extends the memory density of ST's M50FLW family, which is the first to support both firmware hub (FWH) and low pin count (LPC) architectures on the same chip
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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The new M50FLW080 is a 1M x 8bit nonvolatile memory designed to operate on a single 3.0 to 3.6V supply.
Unique auto-detection circuitry determines whether the device is being used in an FWH or LPC environment, by decoding the first four bits of the start time slot, and thereafter operates the appropriate bus protocol with full decoding of either instruction set.
Compatible with Intel LPC Interface Specification Revision 1.1 for LPC and FWH mode, the device is supporting multibyte program (up to 4bytes in a single operation) and multibyte read (up to 128byte in a single operation).
The dual-interface capability simplifies both design and production for PC manufacturers, offering great flexibility and reducing inventory requirements and risk.
LPC is a flexible 33MHz interface which will replace the earlier ISAbus in the majority of new PCs within the next year or two.
The firmware hub protocol (FWH) is an Intel proprietary protocol derived from the LPC specification.
In addition to the dual interface, this new chip offers a thin granularity for erase and program very suitable for BIOS parameters.
The memory space is divided into 16 uniform blocks of 64Kbyte each, of which three are divided into 16 uniform sectors of 4Kbyte - device options offer two of these three blocks at the top of the memory map and one at the bottom, or one at the top and two at the bottom.
All blocks and sectors can be erased independently, and can be protected individually to prevent accidental programming or erasure.
For production programming prior to assembly, the address/address multiplexed (A/A Mux) interface is designed to be compatible with current Flash programmers.
Typical quadruple byte programming time is 10us, when using an optional 12V power supply pin that reduces program and erase time.
Samples of the M50FLW080 are available now.
It is supplied in PLCC32, TSOP32 (8 x 14mm) and TSOP40 (10 x 20mm) packages, and is characterised for operation over the -20 to +85C temperature range.
US pricing is $2.40 in quantities of 10,000.
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