Jivaro qualified for post layout simulation flow

Edxact announces that STMicroelectronics has added Edxact's Jivaro parasitic reduction tools to its Post Layout Simulation flow (PLS), in order to speed up simulations of back-annotated netlists.

Edxact has announced that STMicroelectronics has added Edxact's Jivaro parasitic reduction tools to its Post Layout Simulation flow (PLS), in order to speed up simulations of back-annotated netlists.

Jivaro is a family of standalone reduction tools that remodel parasitics data obtained from layout extraction tools before feeding them to simulation tools.

Jivaro's model order reduction techniques outstandingly reduce parasitic file size and data complexity while maintaining accuracy.

ST has added Jivaro as postprocessor to the layout extractors used in some post layout analysis flows for transistor based design.

Supporting all major netlist formats like SPEF, DSPF, SPECTRE or SPICE, Jivaro enabled ST to standardise on one reduction engine for all extraction tools; which enhances interoperability and helps to save flow integration time.

Moreover, unlike integrated reduction algorithms that often lead to undetermined accuracy, Jivaro gives designers the flexibility to accurately control speed-accuracy tradeoffs.

Jivaro covers analog, RF, mixed-signal and digital designs and has been successfully used for various types of circuits.

"We did extensive testing on various designs and in different compression modes; it was very impressive that Jivaro allows accurate back-annotated simulations in a fraction of time we used before, " said Jean-Paul Morin, Analog/RF CAD manager at STMicroelectronics.

"Edxact is focused on one of our major problems in IC design: exhaustive post-layout analysis with complete back-annotated parasitic data.

With the help of Edxact's team, Jivaro was successfully coupled on extraction tools we currently use, so we can expect important productivity gains and improved quality in our backend verification flow".

"We are pleased by STMicroelectronics's commitment", said Mathias Silvant, Edxact President.

"Parasitics from substrate, interconnects and package need to be taken into account in today's sign-off verifications in order to judge on the chance of silicon success and to reduce design cycles.

The remodelling of those huge and complicated amounts of data can only be done efficiently by dedicated tools.

Edxact's expertise spans on layout extraction and simulation for post layout verification and is dedicated on parasitic analysis techniques.

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