ST leads European embedded project

A strategic targeted research project aims to ensure that the European electronics industry continues to maintain its competitive position in embedded systems.

A strategic targeted research project called Vertigo (Verification and validation of embedded system design workbench) aims to ensure that the European electronics industry continues to maintain its competitive position in embedded systems.

The project, launched by the Commission of the European Communities within the IST (Information Society Technology) area of its Sixth Framework Programme, brings together the complementary expertise of STMicroelectronics, one of the world's largest semiconductor manufacturers and a leader in SoC technology; Aerielogic and TransEDA Systems, experts in design verification tools; and four European Universities: Linkopings (Sweden), Southampton (UK), Tallinn (Estonia) and Verona (Italy).

The aim of the project is to develop a systematic methodology to enhance the modelling, integration and verification of architectures targeting embedded systems built on configurable platforms.

Embedded systems are complex electronic circuits that contain one or more microprocessors along with the processors' associated memories and the peripheral circuits that perform special functions.

These functions can include communicating with the outside world using protocols such as USB or CAN.

Unlike PCs and laptops, where the user can choose which programs to install or run at any time, an embedded system performs a particular set of tasks.

As a result the embedded system includes all the electronic hardware of the system as well also its software.

Examples of embedded systems range from low-cost microcontrollers that control power tools or domestic appliances to highly sophisticated SoC devices used in applications such as set-top boxes.

Because today's advanced embedded systems may contain tens or hundreds of millions of transistors, it is not feasible to invest the resources or time to design new hardware for each application.

Instead, platform-based approaches are commonly used in which the hardware for a particular type of application is built by configuring common hardware blocks.

The Vertigo project aims to bridge the gap between system level modelling and verification performed at the transactional level and the traditional RTL (register transfer level) signoff description.

Although Vertigo will not involve behavioural synthesis, the project will facilitate checking the consistency of different transaction level models (TLMs) and the RTL, regardless of which refinement process is used.

The case studies, taken from embedded systems developed by STMicroelectronics, will focus on mixed-level/mixed-language flows, involving both TLM and RTL.

"We hope to achieve several technology breakthroughs with Vertigo", said Umberto Rossi, Head of Functional Verification Support at STMicroelectronics, which is the leader of the Vertigo project.

"The most important of these is the development of expression coverage criteria common to TLM and RTL that are capable of driving system validation between different abstraction levels".

The Vertigo project will investigate several formal techniques that can contribute to different stages of the design-flow modelling and verification (SW, TLM-level, RTL-level, module level, and system level) and integrated with the simulation-based approach (dynamic verification).

An assertion-based verification (ABV) method will be developed that can be used both in static and dynamic verification with emphasis on TLM and the related metrics to measure their coverage.

Finally, the project team will prototype a SW/HW coverification environment, capable of driving the development of SW routines for the purpose of the embedded platform test.

Vertigo will take the roadmaps of public consortia like Accelera as references, for the development of verification standards and OSCI, for the standardisation of TLM.

The Vertigo project began on 1st June 2006 and will run until 30th November 2008.

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