Physical layer interface IP is ready for 65nm

Edited by the Electronicstalk editorial team May 3, 2007

Next-generation 65nm serial-interface IP supports both 3 and 6Gbit/s Serial ATA hard disk drives for mobile and desktop computing applications.

STMicroelectronics is claiming the industry's first successful fabrication of the next- generation 65nm serial-interface MIPHY (multi-interface PHY) physical layer interface IP (intellectual property).

ST designed the macrocell to be integrated with other functions into low power system-on-chip (SoC) devices supporting both 3 and 6Gbit/s Serial ATA (SATA) hard disk drives for mobile and desktop computing applications.

By implementing and verifying the 65nm interface design now, ST is preparing for the migration of SoC products to 65nm technology later this year, sharing with customers the benefit of lower power requirements and smaller physical size.

The proven IP will minimise the time to market for new products and reduce the development costs of new ASICs.

In addition, the multiple standard capabilities (SATA Gen1, Gen2 and Gen3) of the new macrocell will enable faster design validation for different markets and will yield the benefit of larger scale volume production while reducing costs for manufacturers by optimising their engineering resources.

"ST's strategy is to be at the forefront of technology development, providing Best-in-Class solutions to our customers", said Roberto Fantechi, General Manager of ST's Data Storage Division.

"The release of the industry's first 65nm MIPHY gives our customers what they need - an optimised solution for the fastest growing disk drive segment".

The fourth-generation MIPHY is a key IP block in ST's complete HDD IP portfolio that combines proven IP and innovation.

The device is a significant enhancement to the 90nm PHY, achieving a 35% reduction in die sise and 30% reduction in power over the previous-generation IP.

Further architectural improvements in equalisation and transmitter and receiver circuitry have resulted in enhanced jitter tolerance and lower transmit jitter.

These benefits are aimed squarely at the mobile and cost-sensitive desktop HDD PC markets where a key differentiator for system manufacturers is delivering high-performance operation at the lowest power.

ST has developed a complete portfolio of 65nm IP, including this enhanced MIPHY IP and the next-generation read-channel IP, working closely with strategic customers to address their specific requirements, and is planning to integrate blocks from the portfolio into next-generation 65nm SoCs.

Physical layer macrocells perform the high-speed serialisation and deserialisation of data to and from the drive and provide a 20bit-wide parallel interface to the link layer.

In Serial ATA applications, they can perform either host or device operations, and can drive external signals directly without needing additional external components.