Array technology to boost packaging density

STMicroelectronics, Stats ChipPAC and Infineon Technologies are collaborating on next-generation embedded wafer-level ball grid array (eWLB) technology.

STMicroelectronics, Stats ChipPAC and Infineon Technologies have signed an agreement to jointly develop the next-generation of embedded wafer-level ball grid array (eWLB) technology, based on Infineon's first-generation technology, for use in manufacturing future-generation semiconductor packages.

ST and Infineon, two of the world's leading semiconductor makers, have joined forces with Stats ChipPAC, a leader in advanced three dimensional (3D) packaging solutions, to fully exploit the potential of Infineon's existing eWLB packaging technology, which has been licensed by Infineon to ST and Stats ChipPAC.

The new R and D effort, for which the resulting IP will be owned by the three companies, will focus on using both sides of a reconstituted wafer to provide solutions for semiconductor devices with a higher integration level and a greater number of contact elements.

The eWLB technology uses a combination of traditional front-end and back-end semiconductor manufacturing techniques with parallel processing of all the chips on the wafer, leading to reduced manufacturing costs.

This together with the increased level of integration of the silicon's overall protective package, in addition to a dramatically higher number of external contacts, means the technology can provide significant cost and size benefits for makers of cutting-edge wireless and consumer products.

ST's decision to work with Infineon to jointly develop and use this innovative technology, with its greater integration level of package size, marks an important milestone for eWLB on its way to becoming an industry standard for cost-efficient and highly integrated wafer-level packages.

ST plans to use the technology in several products of its ST-NXP Wireless joint venture and in other application markets, with first samples expected by the end of 2008 and production by early 2010.

"The eWLB technology is an excellent complement for our next-generation leading-edge products, especially in wireless applications", stated Carlo Cognetti, Director, Advanced Packaging Technology, STMicroelectronics.

"The eWLB technology sets new milestones in innovation, cost competitiveness and dimensions and we believe that, together with Infineon, we will pave the way to a new powerful package technology platform".

"We are pleased that ST has selected our trend-setting eWLB technology for its IC packaging and see this partnership as a great recognition for the excellence of our technology", stated Wah Teng Gan, Vice President of Assembly and Test at Infineon Asia Pacific.

"With ST as a new partner, and furthermore Stats ChipPAC as a well-known leader in 3D packaging solutions acknowledging our technology, we see a shift in the packaging industry towards the energy efficient and high-performance eWLB technology".

"We are very pleased that Infineon and ST have selected Stats ChipPAC as a joint development partner to develop the next generation of eWLB technology and to manufacture products on both generations of eWLB technology", said Dr Han Byung Joon, Executive Vice President and Chief Technology Officer, Stats ChipPAC.

"The depth of technical expertise at Infineon and ST, combined with the knowledge we have on driving integration technology and flexibility at the silicon level, are essential to delivering this breakthrough technology".

eWLB is a revolutionary packaging technology, introduced by Infineon in the autumn of 2007.

It sets the benchmark in integration level and efficiency and paves the way to providing the industry and end consumers with a new generation of energy-efficient, high-performing mobile devices.

With these new packaging processes the benefits of wafer-level ball grid array (WLB) technology - namely, cost-optimised production and enhanced performance features - can be extended: All operations are performed at wafer level, as with WLBs, signifying concurrent processing of all the chips on the wafer in one step.

The trend-setting package technology sets the benchmark in integration level and efficiency, namely a 30% reduction of dimension compared with conventional lead-frame laminate packages and an almost infinite number of contact elements.

Back to top