Product category:
Communications ICs (Wired)
News Release from: StorLink Semiconductors | Subject: Gemini family
Edited by the Electronicstalk Editorial
Team on 10 August 2006
Dual-CPU network processors deliver up
to 800MIPS
The Gemini family of dual-CPU network processors help designers craft systems that can manage the high-speed data and video now streaming through fibre connections into homes and businesses.
The Gemini family of dual-CPU network processors from StorLink Semiconductors delivers up to 800MIPS With that throughput and its multiple integrated functions, the line lets designers craft systems that can manage the high-speed data and video now streaming through fibre connections into homes and businesses
This article was originally published on Electronicstalk on 24 Dec 2007 at 8.00am (UK)
Related stories
Low-cost FPGA family available in production
Built on TSMC's 65nm low-power process, the Cyclone III family includes devices that are qualified for commercial, industrial and extended temperatures.
Driver drives LED efficiency
STMicroelectronics has introduced a new white LED driver with specific features for small LCD module backlight and high efficiency white LED power supply for portable applications.
Based on dual ARM9 32bit RISC processor cores, the SL3518 packs dual gigabit Ethernet media access controllers, a TCP/IP offload engine, a 128bit encryption engine, dual integrated drive electronics, serial ATA storage interfaces and a hardware RAID engine that supports RAID5.
"Taking aim at applications such as Internet protocol set-top boxes, voice-over-IP gateways, media servers with RAID, networked-attached storage systems and gigabit router gateways, the chips reduce system complexity to just a few logic chips and memory", said Douglas Cheung, Vice President of Marketing and Sales.
"The dual-CPU architecture maximises system throughput while offering designers flexibility for application software development", Cheung said.
StorLink provides a software suite that includes a fully functional stack running on the first CPU and a small-footprint real-time operating system running on the second CPU.
Also able to run on the second CPU are an interprocessor communications layer and a complete development platform for code development and integration.
The hardwired NetEngine protocol accelerator speeds the processing of network address translations; quality-of-service management; IPv4 and IPv6 routing and forwarding; deep packet parsing; and filtering, segmentation and TCP/IP offload.
The dual 10/100/1000 Ethernet controllers let system integrators configure a traditional NAS server system with one or two Ethernet channels, or a NAS server plus router gateway capabilities using one WAN port and one LAN port.
The Layer 2-4 hardware switching and Layer 2-7 packet classification on chip enable high-end router/gateway designs, according to StorLink.
Able to deliver up to 600/200Mbit/s running DES/3DES algorithms or 237/197/169Mbit/s executing 128/192/256bit AES algorithms, the security acceleration engine keeps data moving rapidly through the chip.
• StorLink Semiconductors: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
