Low-volume ASICs take over from FPGAs

Gleichmann Electronics has a new highly functional, easy to design ASIC architecture from NEC.

Gleichmann Electronics has a new highly functional, easy to design ASIC architecture from NEC.

Aimed at low- to mid-volume designs, the Instant Silicon Solution Platform (ISSP) is a highly functional architecture that combines the performance found in leading edge cell-based ASICs with a remarkably easy design flow.

ISSP devices are based on NEC's proven 0.13-micron UX4 ASIC process, which is a five-metal-layer design that has two customisable upper layers to meet individual design requirements.

The bottom three layers are preconfigured with testing technologies like Scan and BScan, removing the complications associated with the design for test (DFT).

Clock domains are also embedded in the base master, eliminating clock-skew issues.

This structure means that ISSP devices do not incorporate the costs associated with resolving deep submicron design issues such as timing and signal integrity.

ISSPs deliver high performance but consume much less power than a comparable FPGA solution.

Nonrecurring engineering (NRE) costs are up to ten times lower than similar cell-based designs since multiple respins of product prototypes are not necessary.

These attributes make ISSP devices ideal for designs that require a higher degree of complexity than a gate array or FPGA solution without the costs associated with cell-based design.

"Gleichmann Electronics has over 100 man years of experience in NEC ASIC design.

We have an NEC approved ASIC design centre in Europe and can use this facility to provide our customers with the highest quality of technical support during the ISSP design process", said Anna Trett, Applications Engineer for NEC at Gleichmann Electronics.

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