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News Release from: Sun Microsystems Microelectronics | Subject: UltraSPARC IIIi
Edited by the Electronicstalk Editorial
Team on 06 November 2001
Asynchronous logic to boost MPU's memory
bandwidth
Sun Microsystems has previewed a new branch of the UltraSPARC III microprocessor family tree.
Sun Microsystems has previewed a new branch of the UltraSPARC III microprocessor family tree Sun Microsystems' distinguished engineer Kevin Normoyle, described the forthcoming version of the UltraSPARC III processor as optimised for high density one- to four-processor server and workstation systems
This article was originally published on Electronicstalk on 27 Nov 2001 at 8.00am (UK)
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"We designed the UltraSPARC IIIi processor to address a one- to four-way multiprocessing sweet spot.
The chip is intended to reduce system costs by integrating previously off-chip subsystems on chip, thereby simplifying system design and reducing part counts.
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The JBUS interface in particular simplifies design of small scale multiprocessor systems by implementing a fast 'goo-less logic' interconnect between processors.
Also, by executing the processor on a new Texas Instruments' 0.13-micron, copper interconnect process, we expect to introduce the chip at a more than 1GHz, clock speed, while keeping power consumption below 60W, an important spec for systems for easy-deployment, high-compute-density systems".
The UltraSPARC IIIi design is based on an UltraSPARC III supplemented with an enhanced set of on-chip features that position the device for design into cost-optimised, high performance one- to four-way multiprocessing systems.
Significant new on-chip elements integrated into the UltraSPARC IIIi processor design include: a 1Myte, four-way associative L2 cache memory; large data and instruction TLBs (translation look-aside buffers) that support a variety of page sizes from 8Kbyte to 4Mbyte; and a DDR memory interface, 266MHz at 16bit wide, controlling up to 16Gbyte per processor Even though the UltraSPARC IIIi design will integrated three times as many transistors (87 million) as the UltraSPARC III (29 million), the UltraSPARC IIIi is expected to dissipate less than 60W of power.
In addition, the design will incorporate low-power consumption operation modes to further reduce power consumption under light loading.
The low peak power figure derives largely through fabricating the chip on a new 0.13-micron, seven-layer metal, copper interconnect, low-K dielectric process available to Sun at Texas Instruments.
The UltraSPARC IIIi processor design also marks the world's first integration of elements of asynchronous logic technology developed at Sun Microsystems Laboratories.
The processor's memory controller includes asynchronous logic-based first-in, first-out (FIFO) circuits in the memory controller input/output section to absorb clock skew variations inherent in tens-of-million transistor class chips.
Although the asynchronous FIFO is a small part of the UltraSPARC IIIi processor's overall design, it is another instance of technology transfer from Sun Labs influencing the company's product designs.
As a technology disclosure, Sun did not announce a timetable for introduction of the UltraSPARC IIIi processor either on its own as an OEM product or as an element in Sun's system products.
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