Product category:
Design and Development Software
News Release from: Synplicity | Subject: Certify 5.0
Edited by the Electronicstalk Editorial
Team on 21 August 2001
Software automatically partitions FPGA
designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes The software can now perform many time consuming tasks automatically, including partitioning, gated-clock conversion and pin multiplexing, shaving days or weeks off of the prototyping process
This article was originally published on Electronicstalk on 16 Apr 2008 at 8.00am (UK)
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Featuring Synplicity's new Quick Partitioning Technology, the Certify software now provides designers with the capability to automatically partition an ASIC design onto multi-FPGA custom boards for the development of ASIC prototypes.
Additionally, Synplicity has enhanced the Certify software's automatic gated-clock conversion and Certify pin multiplexing (CPM) features to increase the speed and performance of ASIC prototypes.
First introduced in May 1999, the Certify software is the industry's first registered transfer level (RTL) prototyping solution that enables designers to create functional hardware prototypes of their ASIC design at the RTL, prior to ASIC synthesis.
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Today, the Certify software is being used by dozens of users to solve their ASIC verification needs.
With the addition of the Quick Partitioning Technology in the Certify 5.0 software, Synplicity has automated one of the most time-consuming processes in prototyping - partitioning.
Traditionally, a designer needed to use the Certify software's guided interactive partitioning feature to partition a design manually.
Following the designer's manual effort, the software would provide users with feedback to assist with any decision-making regarding the design, such as I/O usage and area usage.
With the Quick Partitioning Technology, a user can optionally set goals for area and I/O usage on the FPGAs in the prototype, then run the Certify software to automatically partition the design onto a custom board.
Early benchmark results show typical ASIC designs that are run through the Certify software using Quick Partitioning Technology are able to be automatically partitioned onto a custom board, often in under a minute.
The same design manually partitioned onto a custom board by an experienced designer required several hours or more, on average.
On very complex designs, the savings in partitioning time can be days.
Additionally, when design changes are made during the verification process with the prototype, the functional changes can be made directly to the original RTL and automatically repartitioned resulting in even more time savings.
The new Certify software provides greater flexibility for designers trying to meet specific design requirements by offering both automated and manual partitioning capabilities, or any combination of the two.
This feature enables a designer to either manually place timing-critical blocks in specific FPGAs and then let the Certify software automatically partition the rest of the design, or let the Certify software automatically partition the whole design before manually partitioning parts of the design.
Continuing to speed the prototyping process, Synplicity has enhanced a key ASIC conversion feature already in the Certify software, the ability to recognise additional gated-clock elements in an ASIC when they are converted into an FPGA.
In addition to the logic gate elements previously recognised in the clock tree, the software can now also detect clock trees with inferred and instantiated memories, inferred and instantiated latches, instantiated registers, shift registers, state machines, and counters.
By developing these unique algorithms that enable the Certify software to recognise complex gated-clock elements, Synplicity has eliminated the traditionally time-consuming task of manually converting gated-clock elements.
Additionally, the Certify software's Certify pin multiplexing capabilities have been enhanced to provide users with the flexibility to choose more CPM implementations including off-chip control modules, enabling a wider choice in pin multiplexing between FPGAs.
The CPM feature allows a designer to time divide signals between pins and share I/Os on a device in order to conserve pins.
The additional CPM functionality in the Certify software provides designers with greater flexibility as to what type of time division multiplexing to use in a design.
The Certify 5.0 software is available now for $115,000 for Windows NT, Windows 2000 and Unix (Solaris and HP) operating systems.
Current Certify customers on maintenance will be upgraded at no additional cost.
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