Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify Pro/Cynthesizer
Edited by the Electronicstalk Editorial
Team on 21 November 2001
Design and verification path from C++ to
PLDs
Synplicity and Forte Design Systems have announced the availability of the industry's first complete design and verification path from C++ to programmable logic implementation.
Synplicity and Forte Design Systems have announced the availability of the industry's first complete design and verification path from C++ to programmable logic implementation As a result of the companies' joint development efforts, designers can use Forte's Cynthesizer C++-to-HDL product and verification suite with Synplicity's Synplify Pro RTL synthesis solution to synthesise C++ code into a gate-level netlist for a broad range of programmable logic devices (PLDs) from leading vendors, including the Excalibur embedded processor solutions now available from Altera
This article was originally published on Electronicstalk on 16 Apr 2008 at 8.00am (UK)
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Also, Altera is to collaborate with Synplicity and Forte to optimise this flow and endorse Cynlib C++ as an alternative design language for system-on-a-programmable-chip (SoPC) designs.
Using this integrated solution for design and verification at a higher level of abstraction, PLD designers can take advantage of the high-performance flow as well as improved verification productivity through use of sophisticated C++ testbenches and fast, unlicensed simulation.
A direct design path from C++ to PLDs enables designers to meet stringent time-to-market requirements while improving productivity and lowering design risk and costs.
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"Traditionally, system architects and hardware designers have been working in different languages at different levels of abstraction, making it impossible to reuse valuable design and verification knowledge", said Brett Cline, vice president of marketing at Forte Design Systems.
"As PLDs have become more complex, this has become a serious design bottleneck.
Using Forte's GigaScale design and verification products, including Cynthesizer with the Synplify Pro software, design teams now have a unified flow from high-level architecture models through to gates with a consistent testbench environment throughout the process.
We are excited to work with Synplicity to significantly reduce overall design and verification times with this unique flow".
Joe Gianelli, director of business development and strategic alliances at Synplicity, said, "We have worked closely with Forte to enable smooth interoperability between our products because we believe C++ offers many benefits for programmable logic designers.
We also believe the integration between our Synplify Pro software and Forte's popular Cynlib C++-based solutions provides the industry's first complete design and verification path from C++ to programmable silicon and can help hardware designers maintain high-performance solutions while accelerating the design of electronic systems from concept to implementation".
Tim Southgate, vice president of software and tools marketing at Altera, added: "One of the primary benefits of an SoPC solution is the ability to implement sections of a design as either software or hardware, depending upon system performance objectives.
Altera is committed to working with Synplicity and Forte Design to provide a robust C++ to PLD design flow that makes this powerful flexibility available to our customers.
Altera's Excalibur embedded processor solutions are here today to take advantage of these exciting new capabilities".
The collaboration between Synplicity and Forte provides a smooth and reliable flow that allows an engineer to enter a design specified in Cynlib C++, Forte's open source C++ class library, directly into Synplicity's Synplify Pro software to obtain a gate-level netlist.
The Synplify Pro software automatically interfaces with the Cynthesizer software to transform the C++ code into intermediate hardware description language (HDL) code and then a highly optimised gate-level netlist for the target PLD.
Synplicity's Synplify Pro synthesis software with an optimised interface to Forte's Cynthesizer software is now available.
Current customers on maintenance will be upgraded at no additional cost.
Forte's GigaScale design and verification products are now available.
Cynlib is available for free under an open source license at www.ForteDS.com.
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