Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify V2.2
Edited by the Electronicstalk Editorial
Team on 13 December 2001
Productivity and performance up for ASIC
design
Synplicity has upgraded its Synplify ASIC software with several productivity and performance improving features.
Synplicity has upgraded its Synplify ASIC software with several productivity and performance improving features The new Synplify ASIC software version 2.2 now features an in-place optimisation capability that enables designers to improve the performance of their gate-level netlist without impacting the downstream place-and-route tools
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
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The in-place optimisation feature enables a designer to adjust cell sizes based on back-annotated.sdf and setLoad information from the place-and-route tools.
This capability within the Synplify ASIC software fixes performance and/or design rule violation issues that otherwise would need to be fixed in more cumbersome ways.
Synplicity also enhanced the core synthesis engine within the Synplify ASIC software by expanding its module generation capabilities, improving the quality of results obtained by the software without requiring extensive scripting, design manipulation or tool settings.
Additional enhancements in version 2.2 of the Synplify ASIC software include: improved interoperability; faster runtimes; and expanded platform support, including HP-UX 11.0, Linux (RedHat 7.1) and Solaris 2.8.
The Synplify ASIC software is available now for Linux (Red Hat 7.1), HP-UX 11.0, Sun Solaris 2.7/2.8 and Windows NT 4.0, Windows 2000 operating systems.
Through 2001, existing Synplicity customers can purchase the Synplify ASIC software for half the list price.
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