Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify Pro
Edited by the Electronicstalk Editorial
Team on 08 April 2002
PLD design software adds Verilog-2001
support
Synplicity has enhanced its Synplify Pro PLD synthesis software with support for the Verilog-2001 standard and support for new devices and new operating systems.
Synplicity has enhanced its Synplify Pro PLD synthesis software with support for the Verilog-2001 standard and support for new devices and new operating systems The latest version of the Synplify Pro software also includes several quality of results (QoR) improvements and enhancements to its incremental timing engine and automated register retiming feature, providing designers with added productivity and performance-improving benefits
This article was originally published on Electronicstalk on 16 Apr 2008 at 8.00am (UK)
Related stories
FPGA software brings IP into line
Allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then implement it into a variety of FPGA devices.
FPGA support provides productivity boost
The Virtex-5 FXT platform comes with up to two PowerPC 440 processor blocks, a DSP and high-speed serial capabilities to deliver a comprehensive system integration platform
"We believe our Synplify Pro software continues to raise the bar for synthesis products by providing timely support for important new standards and offering the best quality of results for device families such as Altera's Stratix and Xilinx Virtex-II Pro", said Andy Haines, vice president of marketing at Synplicity.
"Support for the Verilog-2001 standard within the Synplify Pro software enables our customers to use the numerous benefits provided by the design language.
With the additional new device support, OS support and its QoR enhancements, we believe the Synplify Pro software is an ideal choice for designers of highly complex designs who need to achieve the highest level of performance quickly".
Further reading
Synthesis software support for new FPGAs
Synplify Pro FPGA synthesis software is available for use with Altera's low-cost Cyclone III FPGAs.
Synthesis software is optimised for Stratix III
Synplicity has upgraded its industry-leading Synplify Pro FPGA synthesis and Synplify DSP true DSP Synthesis software to support Altera Corp's new low-power, high-performance Stratix III FPGAs.
Synthesis software is ready with FPGA support
Synplify Pro synthesis software supports the newest members of the Xilinx Virtex-5 family of 65nm FPGAs.
The latest version of the Synplify Pro software supports the new Verilog-2001 standard, an enhanced version of the Verilog design language.
The Verilog-2001 standard offers many significant new features including greater support for configurable intellectual property (IP) modelling, deep-submicron accuracy and design management.
With the new Synplify Pro software, customers can take advantage of powerful new features in Verilog-2001 such as 'generate' and signed arithmetic expressions, which may be applied to registers, nets, function returns and literals.
Other Verilog-2001 features supported in the Synplify Pro software include: exponent power operator, comma-separated sensitivity list, combinatorial logic sensitivity, automatic width extension past 32bit and ANSI-style port lists.
Driven by proprietary Behaviour Extracting Synthesis Technology (BEST) algorithms, Synplicity's synthesis solutions can deliver optimal circuit performance with the most efficient area utilisation.
The Synplify product's BEST technology extracts designer intent from HDL code by inferring complex memories, finite state machines (FSMs) and advanced mathematical functions then efficiently maps them to device-specific hardware resources.
Additionally, with this new release, Synplicity has built on its fast, incremental timing analysis engine and automated register re-timing feature.
The high-capacity timing analysis engine makes timing estimations even more accurate, producing highly optimised circuits with fewer design iterations.
With automatic re-timing, the Synplify Pro software eliminates the labour-intensive process of analysing critical paths and changing HDL code to balance delay and can automatically reposition registers within combinatorial logic to balance routing and ultimately improve circuit performance.
Synplicity has advanced its support in the Synplify Pro software for Altera's Stratix device family enabling rapid and efficient implementation using specialised optimisations to take advantage of the dedicated multiply accumulate (MAC) functions and TriMatrix memory blocks in these high-performance devices.
The software features several QoR improvements for Xilinx's Virtex, VirtexE and Virtex II devices, including auto mapping of ROMs to BlockRAMs and pipelined block multiplier support.
These QoR improvements enable designers to increase device performance while improving the utilisation of dedicated chip resources, resulting in reduced implementation.
The Synplify Pro software also offers new device support for Actel's ProASIC Plus, Lattice's ispGDX2 and isp5000MX, and Xilinx's CoolRunner II and Virtex-II Pro FPGA families.
The Synplify 7.1 and Synplify Pro 7.1 synthesis solutions are available now.
Current customers on maintenance will be upgraded at no additional cost.
The Synplify and Synplify Pro solutions are also available for Windows XP and Linux (RedHat 7.2) operating systems.
• Synplicity: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
