Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify ASIC
Edited by the Electronicstalk Editorial
Team on 14 May 2002
ASIC software boosted to handle more
complex SoCs
Synplicity has enhanced its Synplify ASIC software, easing the flow for designers to achieve high quality of results for complex SoC designs.
Synplicity has enhanced its Synplify ASIC software, easing the flow for designers to achieve high quality of results for complex SoC designs The Synplify ASIC software now includes Synplicity's new MultiPoint synthesis technology as well as several new features to improve quality of results (QoR) and runtime for high-performance ASIC design including case analysis and enhanced support for flows with Verplex Systems and LogicVision
This article was originally published on Electronicstalk on 20 Feb 2004 at 8.00am (UK)
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The MultiPoint technology delivers a productivity-focused, scalable, memory efficient design methodology for optimising across and within partitioned boundaries for large ASIC designs.
"We believe the integration of the MultiPoint synthesis technology within our Synplify ASIC software addresses the most important challenges encountered by our customers such as incremental synthesis, full chip-level performance optimisation and design team productivity", said Andy Haines, vice president of marketing for Synplicity.
"We also believe our enhanced ability to quickly synthesise very large SoC designs while maintaining high quality of results gives us a strong and unique advantage over competitive approaches.
Further reading
Improved quality of results for ASIC design
The latest version of the Synplify ASIC software from Synplicity provides designers of complex ASICs and SoCs with advanced timing, area and runtime performance.
SoC tape-out success for Canon
Canon has successfully used Synplicity's Synplify ASIC synthesis software to tape out a complex system-on-chip design.
Synthesis extended to IBM ASICs
Synplify ASIC synthesis software is now qualified for use by IBM's ASIC customers.
With our new technology, we expect to address a broad segment of today's designs and deliver a highly scalable solution for future design challenges".
With this new version of the Synplify ASIC software, customers can now employ MultiPoint synthesis technology to address large complex ASIC designs with better QoR and significantly faster runtimes than other synthesis methodologies.
With the new MultiPoint technology, the Synplify ASIC software uniquely creates interface logic models (ILMs) based on user-defined "compile points", or instructions to the synthesis tool for modeling and synthesising a particular portion of the design.
As the full design is synthesised, a new difference-based incremental synthesis capability allows parts of a design to remain unchanged while others are synthesised.
This approach eliminates the need for resynthesis that is common to time-stamp-based incremental flows by only re-synthesising design entities that will have a different gate-level netlist due to code, property, or constraint changes.
Unlike other incremental flows where cross-boundary optimisations are difficult,the Synplify ASIC software's flow does not compromise design performance because it can optimise across design partitions.
This is especially important for integrating intellectual property (IP) into a design.
The Synplify ASIC software can now automatically model the IP and use the timing information for synthesis, improving delay QoR and runtime.
For designs with replicated logic or IP blocks, Synplify ASIC software customers can control how each unique instance is treated in terms of boundary optimisations, without the runtime penalty of resynthesising each instance.
The newest release of the Synplify ASIC software also delivers traditional top-down and bottom-up flows, enabling designers the flexibility to implement the most appropriate flow to meet their design requirements.
Also new in Synplify ASIC 2.3 is the ability to perform case analysis for optimisation of complex designs.
Case analysis allows the user to specify constant values to be used on some signals and the rest of the design is optimised taking those constant values into consideration.
This eliminates the need for slower, less integrated approaches such as using external timing analysis tools or having to set up multiple projects to cover all conditions.
Synthesising the design hierarchy all at once in a top-down design flow can help deliver the best design performance.
Previous versions of the Synplify ASIC software were capable of synthesising up to two million gates in a single top-down run, versus a few hundred thousand gates with other synthesis tools.
By incorporating the MultiPoint technology into the Synplify ASIC software, Synplicity builds on the product's memory efficient architecture, dramatically improving design capacity and allowing designers to synthesise complex designs top-down with runtimes up to 15x faster than a bottom-up design flow.
This memory efficiency also reduces design costs by reducing the need to invest in systems with large amounts of physical memory.
Interoperability between design tools is critical to a high-productivity design flow.
In developing the Synplify ASIC 2.3 software, Synplicity worked closely with LogicVision and Verplex Systems to further improve interoperability between the Synplify ASIC software and the companies' embedded test and equivalency checking software.
The Synplify ASIC software can automatically create assertion files for Verplex's products to ease the process of formal verification.
Flow testing using the LogicVision test products has also been performed during the development of the Synplify ASIC 2.3 software.
The Synplify ASIC software version 2.3 is available now for Linux (Red Hat 7.1), HP-UX 11.0, Sun Solaris 2.7/2.8, Windows NT 4.0 and Windows 2000 operating systems.
Current customers on maintenance will be upgraded at no additional cost.
Customers interested in evaluating the software can do so with Synplicity's "express evaluation" toolkit, which enables a designer to complete a four-step evaluation of the software, including installation and training, within a day.
The toolkit provides all of the basic information needed to conduct a hands-on evaluation of the Synplify ASIC software including an evaluation copy of the software, a design tutorial, a test case design and all of the necessary design libraries.
The kit is available by contacting your local Synplicity sales office.
(This was Electronicstalk's Top Story on 13 May 2002).
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