Product category:
Design and Development Software
News Release from: Synplicity | Subject: MultiPoint synthesis technology
Edited by the Electronicstalk Editorial
Team on 14 May 2002
MultiPoint synthesis technology handles
more gates
Synplicity has developed a novel MultiPoint synthesis technology for multi-million-gate SoC and PSoC integrated circuits.
Synplicity has developed a novel MultiPoint synthesis technology for multi-million-gate SoC and PSoC integrated circuits By providing a high productivity design methodology that is scalable to tens of millions of gates, the new technology addresses design challenges that are emerging as ASICs and PLDs become more complex
This article was originally published on Electronicstalk on 16 Apr 2008 at 8.00am (UK)
Related stories
FPGA software brings IP into line
Allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then implement it into a variety of FPGA devices.
DSP tool eases complex multimedia design
Synplify DSP 3.6 includes new enhancements to architectural optimisations and DSP synthesis methodology, as well as new IP blocks and capacity improvements.
Synplicity intends to deploy the MultiPoint technology within each of its ASIC and PLD synthesis products, and has also upgraded its Synplify ASIC software as the first product to support the MultiPoint synthesis flow.
"SoC and PSoC designs are pushing the limits of existing synthesis methodologies, the result being that designers must expend a lot of manual effort managing synthesis flows that can result in long runtimes and suboptimal design quality", said Ken McElvain, chief technology officer, Synplicity.
"The MultiPoint technology combines the quality of results and ease-of-use of top-down flows with the stability, fast runtimes, and capacity of a bottom-up flow.
Further reading
FPGA support provides productivity boost
The Virtex-5 FXT platform comes with up to two PowerPC 440 processor blocks, a DSP and high-speed serial capabilities to deliver a comprehensive system integration platform
ASIC verification platform proves popular
Confirma is the industry's only complete prototyping solution combining best-in-class hardware and software tools in a tightly integrated, easy-to-use environment.
Software receives FPGA optimisation
Synplify Premier 9.0 gives users accurate timing information and insight into debug performance-related issues immediately after synthesis.
By combining the best of existing methodologies with new technology, we believe we are able to deliver an automated high-productivity incremental synthesis solution for large high-performance designs.
We also believe the MultiPoint technology is a key milestone in our strategy to deliver the best possible results in the shortest amount of time to both ASIC and FPGA designers".
By combining new technology with the best of existing design methodologies, Synplicity's MultiPoint technology enables a superior methodology for the most critical design flow requirements.
Specifically, MultiPoint synthesis provides better quality of timing and area results, faster runtime, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of intellectual property (IP) blocks.
The MultiPoint technology employs incremental design techniques that enable parts of a design to remain unchanged while others are synthesised.
The technology uniquely creates interface logic models (ILMs) based upon user-defined "compile points", or instructions to the synthesis tool for modelling and synthesising a particular portion of the design.
Unlike other incremental flows where cross-boundary optimisations are difficult, the MultiPoint technology can optimise across design partitions using the same information needed for a top-down synthesis flow, enabling the highest design performance.
To address design team productivity, the MultiPoint technology incorporates a unique difference-based incremental synthesis approach.
This approach eliminates the need for resynthesis that is common with time-stamp-based incremental flows by only re-synthesising design entities that will have a different gate-level netlist due to code or constraint changes.
Products that incorporate the MultiPoint technology also can deliver traditional top-down or bottom-up flows, enabling designers the flexibility to implement the most appropriate flow to meet their design requirements.
The MultiPoint flow also provides a superior solution to integrating IP into a design due to its ability to automatically model the IP and use the timing information for synthesis.
For example, with the MultiPoint technology RTL IP that is instantiated into a design can have logic optimised both inside the IP block and in the adjacent modules without impacting port assignments for the IP core.
If it is a hard IP block (ie gate-level netlist), the MultiPoint technology will automatically model the IP block, thus saving runtime and memory.
For designs with replicated logic or IP blocks, the MultiPoint technology allows the designer to control how each unique instance is treated in terms of boundary optimisations, without the runtime penalty of resynthesising each instance.
For ASIC designers, the MultiPoint technology delivers a methodology for implementing highly complex designs, at a time when deeper submicron processes are driving typical design sizes above a million gates.
According to market research firm Collett International, this year most ASIC designs will be implemented in 0.13- or 0.18-micron process technology and nearly all will include some form of IP or replicated logic.
Existing methodologies - top-down, bottom-up, or a hybrid of the two - cannot handle this growing complexity.
For example, the traditional bottom-up design flow, or synthesising lower modules of a design before synthesising the upper modules, can require many cumbersome scripts and time budgeting, and can inhibit boundary optimisation which leads to suboptimal design performance.
Similarly, synthesising the design hierarchy all at once in a top-down flow is ideal for delivering the best design performance, but is limited by the memory capacity of the computer, as well as long runtimes for synthesising the entire design.
Likewise, emerging programmable SoC devices include capabilities such as complex I/Os and embedded processors, and offer up to 10 million PLD-gate capacities.
With this increase in complexity come design challenges such as meeting timing, longer runtimes and preventing iterations between synthesis and place-and-route.
Programmable logic vendors are responding to customer needs with new incremental place and route capabilities.
Applying an incremental MultiPoint flow to these designs can significantly improve runtimes for both synthesis and place and route.
• Synplicity: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
