Product category:
Design and Development Software
News Release from: Synplicity | Subject: Certify
Edited by the Electronicstalk Editorial
Team on 20 February 2003
Faster route to ASIC prototyping
Synplicity has enhanced its Certify verification synthesis software to ease the ASIC prototyping process and improve quality of results.
Synplicity has enhanced its Certify verification synthesis software to ease the ASIC prototyping process and improve quality of results (QoR) This new version of the Certify software offers advanced ASIC verification capabilities that provide designers with increased visibility into the prototyping process, including gated-clock reporting and source-code level partitioning
This article was originally published on Electronicstalk on 31 Jan 2007 at 8.00am (UK)
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Software speeds ASIC prototype development
Enhancements in the latest version of the Certify ASIC RTL prototyping software package aim to further accelerate the ASIC verification process.
The company also added a new timing engine and timing analysis capabilities, as well as support for Altera Corp's high-performance Stratix devices and the Linux operating system, among other enhancements.
With these enhancements, Synplicity believes designers can realise significant benefits in time savings, a requirement in creating high-performance ASIC prototypes.
"With ever-increasing nonrecurring engineering costs and mask expenses, today's market environment favours cost-effective ASIC verification solutions, driving customers to look at prototypes as an alternative to lower performance or more expensive technologies", said Brian Caslis, Director of Marketing for the Certify product line at Synplicity.
Further reading
Standard board support simplifies prototyping
Synplicity has enhanced its Certify verification synthesis software to offer support for off-the-shelf commercially available prototype boards.
Software automatically partitions FPGA designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
FPGA software brings IP into line
Allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then implement it into a variety of FPGA devices.
"We believe this enhanced version of the Certify software is our highest performance verification synthesis solution to date and that its advanced features will meet the needs of ASIC customers looking for robust RTL prototyping solutions".
Continuing to speed the prototyping process, Synplicity has enhanced the gated-clock capabilities of the Certify software to offer designers greater visibility of gated-clock elements within the prototype.
A new gated-clock reporting feature allows the designer to view detailed reports that highlight specific ASIC conversion results and messages performed by the Certify software to avoid costly timing and performance problems with FPGA-based prototypes.
The enhanced software now includes Synplicity's highest performance synthesis engine available, speeding synthesis time and improving synthesis results.
Synplicity has also added interactive timing analysis capabilities, enabling designers to identify critical paths quickly and perform fast, interactive timing analysis without resynthesising their design.
Continuing Synplicity's commitment to support the leading edge FPGAs, the Certify software now offers support for Altera's high-performance Stratix devices.
Altera's Stratix FPGAs offer a rich set of advanced features, such as dedicated DSP blocks and abundant on-chip memory resources, which can be leveraged for complex ASIC prototype development.
"RTL functional prototyping offers designers substantial time-to-market advantages and enables early system software debugging.
Based on Synplicity's proven synthesis technology, the Certify software delivers a unique solution for our customers designing high-performance FPGAs", said Jim Smith, Director of EDA Vendor Relations at Altera.
"We have worked closely with Synplicity to ensure the enhancements in the Certify software will allow designers to quickly maximise the performance of our high-performance Stratix architecture".
The Certify software is also compatible with the new DN5000K10 Stratix device-based prototyping board recently introduced by The Dini Group, a professional hardware and software design services firm specialising in high-performance digital circuit design and application development and is also one of Synplicity's partners in prototyping.
The quick partitioning technology within the Certify software provides designers with an automated design flow for prototyping with these off-the-shelf, multi-FPGA boards, dramatically reducing time to market.
Mike Dini, President of The Dini Group said, "Synplicity's Certify software is the only software we have found that allows designers to easily develop ASIC prototypes early in the design phase, and it is extensively used among customers of our off-the-shelf prototyping boards.
Using this software along with our new Stratix device-based prototyping board, we expect our customers will be able to quickly and easily develop a high-performance prototype of their ASIC design".
Additionally, Synplicity has enhanced the source-code level partitioning capabilities of the Certify software to allow users to generate RTL code that refers back to the source code for each FPGA after partitioning.
This capability preserves the original source code, even after partitioning.
To further improve design performance, the Certify software also offers enhanced integration with Synplicity's Amplify Physical Optimizer physical synthesis software.
Designers can use the output from the Certify software after partitioning directly in the Amplify software to perform further timing optimisations.
Synplicity has also added support for the Linux operating system, enabling a broader range of designers to take advantage of the Certify software's prototyping capabilities.
In addition to Linux, the Certify software runs on Unix (Solaris and HP), Windows NT, Windows 2000 and Windows XP Pro operating systems.
Other key enhancements to the Certify software include: increased capacity with MultiPoint synthesis technology support for logical hierarchy; addition of support for Synopsys's DesignWare components in both Verilog and VHDL languages; enhanced Verilog 2001 language support; and Xilinx ChipScope Pro support.
The Certify 6.2 software is available now.
Current Certify customers on maintenance will be upgraded at no additional cost.
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