Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify ASIC
Edited by the Electronicstalk Editorial
Team on 20 February 2004
Timing estimation to become placement
aware
Synplicity is to offer timing estimation based on placement and automatic initial floorplanning as an alternative to traditional wireload model-based RTL synthesis in future releases of Synplify ASIC.
Synplicity is to offer timing estimation based on placement and automatic initial floorplanning as an alternative to traditional wireload model-based RTL synthesis in future releases of its Synplify ASIC software The company intends to offer this technology free of charge to customers who are under maintenance at the time of release
This article was originally published on Electronicstalk on 7 Mar 2003 at 8.00am (UK)
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The latest version of the Synplify ASIC software from Synplicity provides designers of complex ASICs and SoCs with advanced timing, area and runtime performance.
This new technology should help users reduce iterations between front-end and back-end design teams and provide more accurate estimates early in the design flow.
Based on the vendor-proven placement and automatic floorplanning technology used in the Amplify ASIC, Amplify RapidChip and Amplify ISSP synthesis tools, the Synplify ASIC software's automatic placement-aware timing estimation will be optimised for fast runtime and small memory overhead.
"This technology is based on direct customer input", said Ken McElvain, Chief Technical Officer, Synplicity.
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"Additionally, we funded independent market research, including focus groups and conjoint analysis studies, which demonstrated that 70% of system designers who hand off their ASIC design to a backend team wanted synthesis and placement integration, but without having to become deeply knowledgeable about physical design and floorplanning.
This market research also showed us that users viewed this as a natural evolution of standard RTL synthesis, and expect to have this feature provided under maintenance when released.
With this announcement today, we believe we continue to demonstrate that we deliver high-value capabilities under maintenance such as power optimisation (automatic clock gating); advanced datapath module generators; RTL, gate level, and placement level graphical debug environment (HDL Analyst and Physical Analyst); and automated RTL floorplanning".
The Synplify ASIC software has been widely adopted for consumer and communications designs, with many customers citing its area reduction capability.
Customer results show the Synplify ASIC software can achieve up to 30% fewer gates than other synthesis tools, and have up to ten times faster runtimes.
Additionally, the Synplify ASIC software takes better advantage of the complex cells in the vendor library, resulting in significantly fewer pin pairs needing to be routed.
These existing capabilities in the Synplify ASIC product lead to faster layout runtimes.
With the addition of placement-aware timing optimisation, the Synplify ASIC tool is expected to offer both fewer and faster iterations for full design closure.
The advantages offered by Synplicity's ASIC synthesis solutions apply to any size of ASIC design.
Synplicity integrated ASIC placement technology in a way that does not significantly increase memory overhead.
One design team using Synplicity's integrated synthesis and placement technology was able to complete a 2.8 million gate design fully top down in less than a day, using a 32bit operating system.
The software also supports 64bit Solaris and Linux operating systems for top-down operation of virtually any size of ASIC.
Synplicity has found that using timing based on an estimated placement instead of traditional wireload models in performing standard RTL synthesis can result in better correlation to final place-and-route results, even if the placement is not passed forward to the layout tools.
The new timing estimation capability in the Synplify ASIC software includes both the global placer as well as the detailed placer currently available in the Amplify ASIC software.
The placer uses a combination of analytical, mincut, iterative improvement and proprietary techniques for generating placement.
Placement is based on an automatically generated initial floorplan.
The global route estimation is done using an obstacle-avoiding Steiner tree heuristic.
The wire delays are computed from the RC network, which is derived from the global route.
Synthesis optimisations are integrated with placement estimation, global route estimation and P and R-aware delay estimation in generating an optimised netlist.
Synthesis based on this improved timing correlation prevents overoptimisation of circuit paths where wireload models would overestimate delay, saving area.
Placement is used only for improved timing estimation and is not provided as an output of the tool.
Users who want to create, analyse and debug placement of their ASIC are encouraged to use the Amplify ASIC software, which includes Synplicity's Physical Analyst feature for placement-level design visualisation.
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