Sensitive approach enables tight timing closure

The latest release of Amplify ASIC software features Synplicity's new router-independent Sensitive Net Analysis and Prevention (SNAP) technology.

The latest release of Amplify ASIC software features Synplicity's new router-independent Sensitive Net Analysis and Prevention (SNAP) technology.

The SNAP technology enables tight timing closure regardless of the backend router used.

First, specific routes in the design that are susceptible to significant timing variations due to possible routing choices are identified.

Once identified, circuit topology around these sensitive nets is modified to remove router choices that lead to poor results.

Synplicity has filed patents for this technology, which will be available in all future versions of Synplicity's ASIC physical synthesis tools (Amplify ASIC, Amplify RapidChip and Amplify ISSP software solutions).

"Most ASIC designers want the flexibility to use 'best-of-breed' tools together without the concern of interoperability problems", said Ken McElvain, Chief Technology Officer, Synplicity.

"Other physical synthesis vendors have made their tools optimised only for their routing technology - in other words, suboptimal for other routing tools.

Conversely, some vendors have suboptimised their synthesis capability, with the claim that their specific placement and routing technology can reclaim the area or timing performance missed by their physical synthesis.

We believe our SNAP technology directly addresses these issues by combining leading area and timing optimisation technology with router-independent correlation to final GDSII".

Synplicity's SNAP technology also addresses the cost of complex ASIC design.

Many design teams are looking today to incrementally improve their design flow, but cannot afford seven-figure retooling costs to move to a complete single-vendor flow.

By using the Amplify ASIC software, designers can incrementally add to their existing design flows to move into high performance ASIC physical synthesis and leverage their existing physical design investments.

In performing physical synthesis on a complex ASIC design, a common issue for designers is that the final routing topology may be quite different from the routing topology assumed by the physical synthesis tool.

Such topology mismatches account for wire-length and parasitics discrepancies, which result in substantial correlation and timing closure issues.

The specific routes that are different between physical synthesis and final routing are referred to as ambiguous routes.

Ambiguous routes are typically multi-fanout nets, where there are numerous possible topologies to connect the driver to all loads.

Routes that cross-congest regions are also at risk, as they have to detour around the congested areas.

Additionally, crosstalk-induced delays typically put long routes at risk as well.

Synplicity developed algorithms that can identify ambiguous routes and compute their "sensitivity".

Sensitivity is a unique metric that assesses the timing impact of route ambiguity against the design constraints.

Ambiguous routes that have high sensitivity must be addressed, as they endanger final correlation and timing closure.

Synplicity has consequently developed specific physical optimisations that can remove ambiguity of sensitive routes, so that the final routing will match the routing assumptions used in physical synthesis.

This new technology provides unique correlation and timing closure benefits regardless of the detail router used to finalise the design.

The Amplify ASIC, Amplify RapidChip and Amplify ISSP software with SNAP will be available in March 2004 on Windows 2000/XP, Red Hat Linux, HP-UX, and Sun Solaris operating systems.

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