Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify Pro 8.0
Edited by the Electronicstalk Editorial
Team on 25 January 2005
FPGA synthesis gains equivalence
checking
Synplicity and Prover Technology have developed an integrated verification flow for Synplicity's Synplify Pro advanced FPGA synthesis product.
Synplicity and Prover Technology have developed an integrated verification flow for Synplicity's Synplify Pro advanced FPGA synthesis product The integrated flow combines the Prover eCheck equivalence checker and the Synplify Pro 8.0 software, enabling users of the Synplify Pro product to routinely employ Prover's formal verification product in their verification flow
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
Related stories
Synplicity adds support for Linux
Synplicity is to add support for the Linux operating system to its entire portfolio of synthesis and prototyping products.
TOPS: synthesis flow fully automated
Synplicity has highlighted details of a second-generation physical synthesis technology for programmable logic designers, the first such technology in the industry
The flow was developed to meet the growing demand for efficient formal verification for mission-critical FPGA applications and ASIC prototyping.
The combined flow automates equivalence checking of Altera and Xilinx FPGA designs, dramatically reducing the need for manual configuration.
As a result, FPGA designers can now leverage a thorough equivalence checking methodology previously only available to ASIC designers.
"As FPGA design complexity continues to increase, it is important that Synplicity offer high-quality equivalence checking to its customers", said Andy Haines, Vice President of Marketing at Synplicity.
"We believe our partnership with Prover Technology and the formal verification flow we have developed together provide our customers a high-quality formal verification solution along with outstanding technical support".
"When using FPGAs for ASIC prototyping or in mission critical systems, it is imperative to ensure that the logic functionality of the device matches the golden RTL", said Marcus Tallhamn, Vice President of Marketing and Business Development, Prover Technology.
"Our joint flow enables designers to achieve functional closure with unparalleled ease of use and automation".
Synplify Pro 8.0 software and Prover eCheck 4.2 are available now.
• Synplicity: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

