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FPGA software supports switch to structured ASICs

A Synplicity product story
Edited by the Electronicstalk editorial team Jan 25, 2005

Synplicity's FPGA synthesis products now support Altera's new HardCopy II device family.

Synplicity's FPGA synthesis products now support Altera's new HarDCopy II device family.

The same leading-edge logic optimisations performed by the Synplify and Synplify Pro products for Altera FPGAs are also applied to the new HardCopy II devices.

Customers designing HardCopy II devices can use their existing Synplify products to achieve high timing performance and area utilisation for these devices.

"Synplicity continues to be an excellent partner for Altera and has a strong track record of delivering best-in-class solutions for our newest FPGAs like Stratix II.

Synplicity is now providing that same level of support for our new structured/platform ASIC solution, HardCopy II", said Danny Biran, Vice President of Product and Corporate Marketing at Altera Corporation.

"As is the case with all our devices, HardCopy II customers using Synplicity's synthesis technology will be able to achieve the highest quality of results while also being able to minimise tool training and development costs".

"With its FPGA front-end design methodology and low cost point, Altera's HardCopy II devices offer customers a unique structured ASIC option", said Andy Haines, Vice President of Marketing at Synplicity.

"For more than two years, Synplicity has been committed to supporting the structured/platform ASIC market with best-in-class design tools and our support for Altera's latest HardCopy II structured ASICs continues this trend".

"Altera's customers will be able to continue using Synplicity's familiar, easy-to-use synthesis software in their HardCopy II design flow with the assurance that they will achieve the results they have come to expect from Synplicity".

Synplicity's Synplify software helps programmable logic designers rapidly achieve aggressive performance objectives.

The Synplify software takes designs written in VHDL or Verilog as input, and compiles, optimises and maps them into efficient, high-performance netlists for all leading CPLD and FPGA devices.

The Synplify Pro software offers high quality of results and fast runtimes along with an expanded feature set optimised to increase performance and productivity for today's complex programmable devices.

Synplify and Synplify Pro software are available now.

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