Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify 8.0
Edited by the Electronicstalk Editorial
Team on 25 January 2005
FPGA synthesis boasts boost to
productivity
Synplicity has unveiled major enhancements to its industry-leading FPGA synthesis software.
Synplicity has unveiled major enhancements to its industry-leading FPGA synthesis software These enhancements are designed to provide users with significant productivity gains through close integration with formal verification, place and route, and debugging products while also improving on the company's unmatched quality of results (QoR) for FPGAs in terms of area and timing performance
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
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The Synplify Pro 8.0 synthesis tool delivers these productivity and QoR improvements through new features and greater integration with other tools in the design flow.
For example, integrated formal verification flow support for Cadence's Conformal and Prover Technology's eCheck equivalence checker software is now provided, enabling the Synplify Pro software's advanced optimisations to be used with popular formal verification software solutions.
In addition, the Synplify Pro software now delivers tighter integration with place and route tools from Actel, Altera and Xilinx, making it easier for users to run place and route after synthesis and manage the results in the Synplify Pro project.
Further reading
Software automatically partitions FPGA designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
Physical optimiser gets the best from FPGAs
Synplicity's FPGA logic synthesis and physical synthesis products can provide full support for the new Xilinx Integrated Software Environment (ISE) 4.1i.
Logic placement speeds synthesis an extra 10%
Synplicity has enhanced its FPGA/PLD synthesis and physical synthesis software with new productivity and performance-improving features designed to enable higher quality of results.
For easy debugging, Synplicity's Identify tool, the only source code debugging product for FPGAs, has also been integrated into the Synplify Pro product.
This latest version of the Synplify Pro software also includes new device support for Actel's newly announced low-cost ProASIC3 FPGAs as well as Altera's HardCopy II family of structured ASICs.
"Synplicity has set the standard in FPGA synthesis for many years and with today's introduction of our newest Synplify Pro software we have taken big steps in improving the productivity of our users, which directly impacts their ability to get their designs to market quickly", said Jeff Garrison, Director of Marketing for FPGA products at Synplicity.
"In addition to the many time saving features, we're seeing significant improvements in timing performance and area reduction, which often enables designers to move to a less expensive device".
The Synplify Pro 8.0 software writes out a verification interface file (VIF) for use with formal verification flows targeting Altera and Xilinx devices.
Popular formal verification tools, such as Prover Technology's eCheck, can now read the optimisations performed by the Synplify Pro synthesis software and perform logical equivalency checking.
The integrated verification flow automates equivalence checking of FPGA designs, significantly reducing the need for manual configuration and providing FPGA designers with an equivalence checking methodology that was previously only available to ASIC designers.
Cadence's Conformal LEC product extends equivalency checking to FPGAs through the Synplicity design flow for Altera and Xilinx devices (as originally announced by Cadence in November, 2004).
The Conformal technology checks the functional equivalence of designs at various critical stages, enabling the designer to quickly identify and correct potential errors.
For designers that want to use the System Verilog language to describe their FPGA designs, the new Synplify Pro software supports a subset of the System Verilog specification in order to further improve designer productivity through higher level coding efficiency.
Support for System Verilog within the Synplify Pro software includes: simplified named port connections using ".name"; implicit port connections using ".*"; and procedural statement support for "always".
In addition, the log file generated during synthesis by the Synplify Pro software is now HTML based, allowing specific sections to be easily navigated and viewed.
Users also have the ability to filter out certain errors and warnings, enabling them to focus only on new errors and warnings that occur with the latest synthesis run, thereby improving productivity.
The Synplify Pro software incorporates a powerful new command line tcl find feature that allows designers to use expressions and operators to find and collect specific elements in their design and then perform operations such as add, union and difference.
With this feature, users can quickly analyse their FPGA design and create very specific design constraints for improved performance.
A true dual-write RAM support feature is also provided to enable the Synplify Pro software to select the correct RAM implementation for the user's target FPGA device.
As FPGA complexity increases, the amount of time spent in debug has increased commensurately.
As a result, Synplicity's powerful Identify RTL debugger has been integrated into the Synplify Pro product allowing users to quickly bring up the instrumentor and debugger tools from within the Synplify Pro software user interface and have the debug files managed through a common project.
In addition to the new major enhancements, the Synplify Pro 8.0 synthesis tool also features timing-driven synthesis support for Actel's new ProASIC3/E FPGAs, as well as Altera's new HardCopy II family of structured ASICs.
"Synplicity has worked closely with Actel over the past year to provide superior synthesis support for our new ProASIC3/E family of FPGAs", commented Saloni Howard-Sarin, Director of Antifuse and Tools Marketing at Actel.
"Features in the Synplify Pro 8.0 software, such as support for advanced global options and forward annotated SDC, will allow customers to achieve their performance and utilisation goals while benefiting from the cost advantages of our new device family".
Jim Smith, Director of EDA Vendor Relations at Altera stated: "The new HTML Log Viewer and TCL Find features in the Synplify Pro 8.0 software give users the power and flexibility to quickly analyse and constrain their designs for optimal performance".
"This enables customers targeting high-performance Stratix II FPGAs and HardCopy II structured ASICs to realise the performance requirements of their design while achieving time-to-market advantages".
Steve Lass, Director, Software Marketing at Xilinx, added: "With its new version of the Synplify Pro software, Synplicity has further improved performance for our industry-leading Virtex-4 family, offering the best synthesis technology available for these devices".
The Synplify 8.0 software is available now.
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