Product category:
Design and Development Software
News Release from: Synplicity | Subject: Identify
Edited by the Electronicstalk Editorial
Team on 18 April 2005
Comprehensive claims for debugging
solution
An enhanced version of the Identify RTL debugger includes several ease-of-use features, delivering customers the most comprehensive debugging solution in the industry.
Synplicity has developed an enhanced version of its Identify RTL debugger software that includes several ease-of-use features, delivering customers the most comprehensive debugging solution in the industry An important member of Synplicity's product portfolio of FPGA design tools, the Identify software combines powerful debug features with the ease of use that Synplicity customers have come to expect
This article was originally published on Electronicstalk on 28 May 2007 at 8.00am (UK)
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Synplicity has enhanced its Identify RTL debugging software to further accelerate FPGA hardware debugging.
Enhancements to the latest version of the Identify software include mixed language support, crosstriggering between multiple instances of the intelligent in-circuit emulator (IICE ) and signal equivalence capability.
Additionally, the debugging solution now offers support for Altera's Stratix II family of FPGAs.
With these enhancements to the Identify software, Synplicity believes users will be able to quickly and easily debug their FPGA designs, resulting in a savings of weeks in debugging time.
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Allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then implement it into a variety of FPGA devices.
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Marty Stainbrook, ASIC Engineer, Emulex Corp, said of Synplicity's debugging solution: "The Identify software has enabled us to trim weeks off our debugging time".
"Our previous method of debugging internal signals on FPGA prototypes was to add probes to the design".
"This approach resulted in time consuming limitations, including few available pins and unpredictable probe routing delays".
"Now with the Identify software, we can instrument entire modules in one go, saving a tremendous amount of time".
"There is no denying the benefits of the Identify software".
The Identify 2.2 software is closely integrated within Synplicity's FPGA design flow, offering designers an easy, yet powerful debugging solution.
Synplicity's Identify Instrumentor software allows designers to annotate directly in their HDL code the signals and conditions they want to monitor, then seamlessly run synthesis and place-and-route to implement the FPGA device.
Once the FPGA has been programmed, the Identify RTL Debugger is run, allowing users to view actual signal values directly in their HDL code and debug a live FPGA, in system, and at the target operating speed.
"The Identify software offers the speed and accuracy of a logic analyser with the convenience and diagnostic capability of a simulator", said Jeff Garrison, Director of FPGA Product Marketing at Synplicity.
"Unlike any other FPGA debug product, the Identify solution allows designers to probe their design and annotate results directly in their HDL source code".
"We work closely with our customers to maintain an easy-to-use methodology, while supporting powerful triggering capabilities that let designers capture and analyse the exact data they need".
The Identify 2.2 software offers more comprehensive features including mixed-language support for customers using both VHDL and Verilog modules within their design.
The use of mixed-language support within the Identify software eliminates the need for designers to manually re-implement an IP module that is written in a language different from the primary language of the design.
The latest version of the Identify software also includes a feature that enables users to crosstrigger between IICEs.
With the Identify 2.2 software, multiple IICE triggers can be combined into a master trigger that controls the buffer.
A master trigger from so many sources across clock domains is a very powerful mode of triggering that allows triggers from an IICE operation in one clock domain to trigger another IICE in another domain.
This feature allows users to find timing problems between domains quickly and easily.
An additional feature to the Identify 2.2 software is its signal equivalence capability.
Currently signal instrumentations do not propagate to different levels of the designs.
The signal equivalence feature within the Identify 2.2 software solves that problem by propagating the signal instrumentation throughout the design so that it is visible across all levels of hierarchy.
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