Product category:
Design and Development Software
News Release from: Synplicity | Subject: Amplify AccelArray Pro
Edited by the Electronicstalk Editorial
Team on 16 June 2005
Physical synthesis speeds structured
ASIC design
Amplify AccelArray Pro software is a physical synthesis solution uniquely optimised for Fujitsu AccelArray structured ASIC devices.
Synplicity's new Amplify AccelArray Pro software is a physical synthesis solution uniquely optimised for Fujitsu AccelArray structured ASIC devices The Amplify AccelArray Pro software is fully qualified by Fujitsu and is integrated into the new AccelArray design kit
This article was originally published on Electronicstalk on 21 Apr 2005 at 8.00am (UK)
Related stories
Software qualifies for Fujitsu platform ASICs
The newest member of the Synplicity Amplify family of structured/platform ASIC products, Amplify AccelArray Pro, has received full qualification from Fujitsu.
Synplicity adds support for Linux
Synplicity is to add support for the Linux operating system to its entire portfolio of synthesis and prototyping products.
The new design kit enables AccelArray customers to dramatically improve the efficiency of their design process and their ability to generate clean, one-pass hand-offs, resulting in lower project investment and greatly reduced risk.
AccelArray from Fujitsu is an innovative structured ASIC device that leverages Fujitsu's proven ASIC design and system-level expertise as well as its IP development technologies to enable customers to achieve high-performance designs with extremely fast design schedules.
An ideal solution for imaging applications that require high-speed processing, as well as for the storage and networking, telecommunications, and industrial automation markets, AccelArray delivers lower power consumption, higher performance, and dramatically reduced development costs.
Further reading
TOPS: synthesis flow fully automated
Synplicity has highlighted details of a second-generation physical synthesis technology for programmable logic designers, the first such technology in the industry
Software automatically partitions FPGA designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
Physical optimiser gets the best from FPGAs
Synplicity's FPGA logic synthesis and physical synthesis products can provide full support for the new Xilinx Integrated Software Environment (ISE) 4.1i.
"By partnering with Synplicity, we were able to provide a design environment that enables customers to maximise the performance, density and time-to-market advantages of AccelArray devices", said Fujio Nakanishi, deputy general manager of the ASIC, network and communication products division of Fujitsu.
"We are pleased to recommend Synplicity's Amplify AccelArray Pro physical synthesis and floor-planning software to Fujitsu's AccelArray customers".
Andy Haines, Vice President of Marketing at Synplicity added: "Our partnership with Fujitsu goes back more than three years, during which time the company announced its full support of our Synplify ASIC tool for cell-based ASIC designs".
"Today's announcement reinforces our common goal of delivering software solutions that meet our customers' most stringent design requirements".
"Our close partnership with Fujitsu allows us to deliver a highly automated, accurate and user-friendly physical synthesis solution for structured ASIC customers using Fujitsu devices".
Developed in close co-operation with Fujitsu, Synplicity's Amplify AccelArray Pro software provides a single integrated design environment, allowing AccelArray structured ASIC customers to floorplan their design, perform physical synthesis, interactively analyse and modify their AccelArray design based on physical results and generate a legalised placement that meets handoff criteria.
At the time of hand-off, Synplicity's patented SNAP (sensitive net analysis and prevention) technology has additionally configured the circuit topology to provide predictable routing.
The software thus generates a legally placed gates design, with timing closely correlated to the timing of the final routed design.
This close correlation allows Fujitsu to quickly close timing after hand-off, eliminating iterations between the designer and Fujitsu.
The new AccelArray design kit with Amplify AccelArray Pro software is available for immediate delivery.
• Synplicity: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
