Software accelerates platform ASIC design

New versions of Amplify RapidChip and Amplify RapidChip Pro software deliver higher quality of results and enable users to perform fast timing closure for their RapidChip devices.

Synplicity has announced the 5.0 version of its Amplify RapidChip and Amplify RapidChip Pro software, an enhanced solution within its Amplify family of customised physical synthesis software.

The Amplify RapidChip software, which was uniquely developed for LSI Logic's RapidChip platform ASIC devices, features several new optimisations that deliver higher quality of results and enable users to perform fast timing closure for their RapidChip devices.

The latest version of the Amplify RapidChip Pro software offers customers a combined physical synthesis and floorplanning solution that provides significant performance and time-to-market improvements for designers using LSI Logic's RapidChip platform ASIC devices.

New features in the Amplify RapidChip Pro software include an advanced macro placer and the Affinity Placer.

For more than two years, Synplicity has worked closely with the major structured/platform ASIC vendors to develop customised synthesis and physical synthesis software that targets the individual vendor's unique architecture.

Through such collaboration, Synplicity has become the primary EDA tool provider of architecture-specific implementation tools for this growing market.

The customised physical synthesis solutions Synplicity jointly developed with the vendors offer users several advantages over conventional ASIC design flows, including enabling a one-pass handoff to the structured/platform ASIC vendor.

The Amplify software enables users to reduce their entire structured/platform ASIC-based design time by up to 50% compared with traditional ASIC flows.

"We share a common mission with LSI Logic to enable designer productivity and speed time to market", said Andy Haines, Vice President of Marketing, Synplicity.

"Synplicity has worked closely with LSI Logic's RapidChip engineering team for more than two years to create a customised physical synthesis solution that uniquely targets the RapidChip architecture and sets a new standard for custom logic designer productivity".

"We believe that RapidChip customers using Synplicity's Amplify RapidChip Pro software will receive an easy-to-use streamlined design flow that to help them achieve the results they have come to expect from Synplicity".

The Amplify RapidChip Pro software offers an enhanced macro placer that automatically and efficiently places small macros and memory blocks within LSI Logic's RapidChip architecture.

The new enhanced macro placer within the Amplify RapidChip Pro software reduces the need for customers to manually floorplan the memory and macro blocks within the RapidChip device, while also minimising design iterations.

The result is users are able to converge on timing closure much quicker and obtain excellent quality of results.

Synplicity has found that by using the new macro placer total wire length (TWL) for routing, the design can be reduced up to 18%, providing significant timing and congestion improvements in the design.

Also in the latest version of Amplify RapidChip Pro is the new Affinity Placer.

The Affinity Placer provides users a preplacement constraint mechanism to keep conflicting paths from interfering with each other's performance.

The Affinity Placer can yield significantly higher quality of results for circuit placement in RapidChip platform ASIC devices, specifically to manage timing closure for designs using the RapidChip technology advanced high speed I/Os.

"Our RapidChip platform ASIC devices have an innovative architecture that provides design flexibility with excellent performance and low power consumption", said Ameesh Desai, Senior Director of Design Technology, LSI Logic Corporation.

"We've worked very closely with Synplicity to ensure that Amplify RapidChip Pro has the detailed knowledge of our architecture that is required for creating performance-optimised platform ASIC solutions".

"We believe the enhancements to the Amplify RapidChip Pro software will further enhance our customer's ability to achieve rapid timing closure and significantly reduce manual floorplanning".

The Amplify RapidChip Pro software features several other enhancements that improve quality of results for RapidChip devices, while improving overall area and placement utilisation.

These enhancements include support for LSI Logic's memory architecture and a RapidChip device-specific floorplan input checker.

The Amplify RapidChip and Amplify RapidChip Pro software both offer additional capability to accelerate closure of complex RapidChip designs.

LSI Logic's latest slices contain an advanced memory architecture for which the Amplify RapidChip software has been customised to achieve optimal results in floorplanning, physical synthesis, and placement.

The design flow now has a seamless transfer of information from the RapidWorx memory selector to Amplify RapidChip.

The floorplan input checker validates the input and makes sure it is a "legal" floorplan before committing it to physical synthesis.

This feature enables users to catch design problems much earlier in the design flow and reduce the number of iteration.

The Amplify RapidChip Pro software is available now.

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