Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify Premier
Edited by the Electronicstalk Editorial
Team on 06 October 2005
Graph-based synthesis speeds FPGA design
Synplicity has expanded its Synplify family of FPGA synthesis tools to address the design challenges presented by today's complex FPGA devices.
Synplicity has expanded its Synplify family of FPGA synthesis tools to address the design challenges presented by today's complex FPGA devices Synplicity's Synplify Premier software offers FPGA designers an integrated environment that features Synplicity's industry-leading FPGA synthesis technology, a pushbutton physical synthesis flow using its proprietary graph-based physical synthesis technology and powerful RTL debug based on its popular Identify RTL debugger product
This article was originally published on Electronicstalk on 28 Jan 2008 at 8.00am (UK)
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With the Synplify Premier software, Synplicity continues its commitment to delivering new innovative technologies for designing the latest generation of programmable logic devices.
The backbone of the Synplify Premier software is Synplicity's new graph-based physical synthesis technology, an automated, single-pass design flow that delivers superior timing performance, dramatically improved timing correlation, and reduced design cycle time and iterations.
Using this graph-based approach to physical synthesis, designers are able to close on aggressive timing requirements much faster while achieving a performance improvement of up to 20% compared with logic synthesis alone.
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Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
"Synplicity was the first to deliver physical synthesis for FPGAs, and with our next-generation graph-based approach to physical synthesis, Synplicity continues its commitment to technology innovation", said Andy Haines, Vice President of Marketing at Synplicity.
"Better timing closure and physical optimisations all hinge on highly accurate timing estimations before running place and route".
"We believe our new graph-based physical synthesis technology delivers the accuracy needed to reduce design iterations and meet aggressive performance goals quickly and reliably".
Synplicity's new graph-based physical synthesis technology, featured in the Synplify Premier software, creates a detailed routing resource graph of pre-existing wires, switches and placement sites used for routing an FPGA.
With this graph, optimisation and placement are driven by wire delay and actual availability of resources, rather than by measuring distance alone.
Graph-based physical synthesis merges optimisation, placement and routing to ensure critical paths of a design use the fastest routing resources available.
This pushbutton physical synthesis flow generates a fully placed and physically optimised netlist ready for input to the FPGA vendor's routing tool.
In using the Synplify Premier software in a recent project, Bjorn Halfen, Senior Design Engineer at Dolphin Interconnect Solutions, said of the software: "By using the graph-based physical synthesis technology in Synplify Premier we were able to reduce the delay in our complex Xilinx Virtex-II Pro design from 14 to 8ns without any floorplanning".
By taking a graph-based approach to physical synthesis, the Synplify Premier software is able to deliver highly accurate timing correlation between the estimated and final post place and route (P and R) results, providing faster timing closure and reducing the number of iterations between synthesis and P and R.
Internal testing suggests that 90% of the timing predictions produced by Synplify Premier software are within 10% of final post P and R timing, and 70% are within 5% of final timing.
The automated, pushbutton flow requires no additional expertise from the FPGA designer and does not require a floorplan or other physical constraints to be used.
The automated graph-based physical synthesis flow within the Synplify Premier software currently supports Xilinx Virtex-4, Virtex-II Pro and Spartan-3 FPGA devices.
Steve Lass, Director, Software Marketing at Xilinx said: "With the Synplify Premier software, Synplicity continues to deliver on its strategy of offering solutions that provide excellent quality of results and productivity advantages".
"We are pleased to recommend the Synplify Premier software to our customers that require fast timing closure in our FPGAs".
In addition to industry-leading synthesis results, the Synplify Premier software also provides a rapid method of finding functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware.
Synplicity's integrated debugging software allows designers to annotate signals and conditions they want to monitor directly in their RTL code.
Nodes that may be used as breakpoints and watch points are displayed for easy menu-driven instrumentation, and then seamlessly run through synthesis and P and R to implement the FPGA.
Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed.
The tool offers advanced triggering that helps pinpoint design problems that could take a simulator days or weeks to uncover.
As ASIC designers increasingly depend on FPGAs to prototype all or part of their designs, there is a need for a synthesis and verification environment that can take HDL code written for an ASIC and efficiently implement it in an FPGA.
Synplify Premier software accommodates this by performing gated clock conversion and handling generated clocks and Synopsys DesignWare components automatically.
The Synplify Premier software addresses single FPGA prototypes, while Synplicity's Certify RTL prototyping product enables multiple FPGA prototypes with advanced partitioning and pin multiplexing technology.
The Synplify Premier software is available now.
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