Prototyping family extends to single-chip designs

Synplify Proto is the first prototyping tool to address the need for single FPGA prototyping by integrating logic synthesis with debugging capabilities.

In support of the rapidly growing ASIC prototyping market, Synplicity is expanding its FPGA-based ASIC prototyping solution offerings by introducing Synplify Proto single-chip ASIC RTL prototyping software.

The Synplify Proto software is the first prototyping tool to address the need for single FPGA prototyping by integrating logic synthesis (Synplicity's Synplify Pro Advanced FPGA synthesis) with debugging capabilities (Synplicity's Identify RTL debugger).

The product also includes a utility to convert instantiated Synopsys DesignWare IP in the customer's ASIC RTL code to synthesiseable RTL equivalents for the FPGA.

Synplicity used its extensive prototyping expertise to develop the Synplify Proto software and to provide customers who prototype using a single FPGA with similar performance benefits as its industry leading multi-FPGA solution, Certify ASIC RTL prototyping software.

The Certify software is a high-performance solution that enables ASIC prototyping across multiple FPGAs.

Features of both prototyping tools include automatic recognition and translation of ASIC elements, such as gate-level components or gated-clock tree structures, to an appropriate form for FPGA implementation.

The tools make ASIC prototyping significantly easier, shorten prototype development time, improve prototype performance, and enable faster time-to-market.

The Synplify Proto product was engineered so that no RTL code modifications are required to bring the entire ASIC RTL source code, or a chosen portion of it, into FPGAs for the purpose of prototyping.

The designer can then use the debugging tool to find and solve problems within their FPGA prototype.

This provides a closed-loop environment for error detection and error correction, dramatically shortening the time to debug the ASIC RTL To aid in determining design functionality the tool also includes Synplicity's HDL Analyst design visualisation environment.

Designers can use this feature to cross-probe between the RTL source code and the schematics of the design.

This is a critical capability for designers needing to prototype only a portion of their design.

"According to Collette International and our own market research, 30-40% of chip designs are prototyped using FPGAs".

"Due to the increasing costs and risk of error on complex ASICs, we expect this number to grow significantly over the next few years", said Andy Haines, Vice President of Marketing at Synplicity.

"We believe Synpilcity is in a unique position to serve ASIC prototyping designers whether they prototype their entire design or are among the growing number who prototype just a portion of the design".

"With our popular Certify software, we continue to support those who prototype using multiple FPGAs".

"And now with the introduction of the Synplify Proto software, and the expansion of our Partner in Prototyping programme, we provide support to those who prototype using single FPGAs as well".

Synplicity's Synplify Proto software is now available.

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