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Design and Development Software
News Release from: Synplicity | Subject: IP encryption flow
Edited by the Electronicstalk Editorial
Team on 21 June 2006
Free flow protects the industry's IP
A free, nonproprietary IP encryption flow enables industry-wide interoperability.
Synplicity has developed a free, nonproprietary IP encryption flow that permits industry-wide interoperability Synplicity is offering this methodology to the EDA, IP and end-user communities as a means to address the challenges designers face when using protected IP in their design flows, which are often made up of tools from several different EDA providers
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
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Synplicity will host a breakfast panel the morning of 25th July at the 2006 Design Automation Conference in San Francisco to discuss this open IP encryption flow and methodology.
Panel members will comprise representatives from ARM, Cadence Design Systems, Lattice Semiconductor, VSI Alliance (VSIA), Xilinx and Synplicity.
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This proposed IP encryption methodology, which is applicable to both FPGA and ASIC design flows, should significantly simplify the integration of IP for designers.
Some EDA companies have attempted to offer their own proprietary encryption schemes, but they did not satisfy user needs because design flows typically consist of tools from more than one EDA vendor.
The proposed nonproprietary methodology would allow IP vendors to create a single version of the encrypted data that can be used by tools from multiple EDA vendors.
"The open IP encryption environment proposed by Synplicity would facilitate the use of protected IP throughout the design flow, from IP vendor to EDA vendor to silicon supplier", stated Gary Meyers, President and CEO at Synplicity.
"This methodology aims to create a standard for encryption and decryption in electronic design flows, which would support industry-wide interoperability, for any application where FPGAs or ASICs are used".
The methodology uses openly available, well-tested, and Government approved encryption methods combined with an encryption embedding mechanism proposed by Cadence for the next revision of IEEE1364-2005.
The methodology permits IP vendors to choose how far encryption persists through the design flow and includes the option of encryption all the way to the semiconductor.
This generic cryptosystem approach combines symmetric encryption (also called symmetric cipher, such as DES, 3DES and AES) with asymmetric encryption (also called public key encryption, such as RSA).
"A standard mechanism for IP encryption will permit users to easily employ encrypted IP with a wide variety of design flows", added Meyers.
"IP vendors will benefit from the protection of their proprietary ideas while enjoying the benefits of its widespread accessibility".
"EDA vendors will be able to offer tools that accommodate the increasing variety of IP without having to deal with hundreds of different protection mechanisms".
"In addition, the semiconductor vendors, who often provide IP, will also benefit from the shorter design times made possible by the extensive use of IP".
To provide more information on the new methodology, Synplicity will host a panel discussion during the Design Automation Conference entitled: "An industry standard IP protection system for EDA tool flows".
Panellists will include representatives from ARM, Cadence Design Systems, Lattice Semiconductor, Synplicity, VSIA and Xilinx, and will be moderated by Gabe Moretti.
The panel session will be held on Tuesday 25th July 2006 from 0730 to 0915 in Room 302 of the Moscone Center.
The panel session is open to all DAC delegates.
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