Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify Premier 9.0
Edited by the Electronicstalk Editorial
Team on 28 January 2008
Software receives FPGA optimisation
Synplify Premier 9.0 gives users accurate timing information and insight into debug performance-related issues immediately after synthesis.
Synplicity's Synplify Premier software has been enhanced to provide more time to market benefits to designers using high-density FPGAs In release 9.0, the graph-based physical synthesis technology has been optimised for Xilinx Virtex-5 FPGAs to deliver exceptional timing closure, analysis and debug for these devices
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
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Synplicity has highlighted details of a second-generation physical synthesis technology for programmable logic designers, the first such technology in the industry
This latest release extends the graph-based physical synthesis technology which has been implemented for Xilinx Spartan-3, Virtex-II Pro and Virtex-4 FPGAs for more than two years.
Synplicity has extended these benefits to FPGA designers targeting Altera Stratix-III, Stratix-II and Stratix-II GX FPGAs, through the company's Synplify Premier Beta programme.
Synplify Premier 9.0 gives users accurate timing information and insight into debug performance-related issues immediately after synthesis.
Further reading
Software automatically partitions FPGA designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
Physical optimiser gets the best from FPGAs
Synplicity's FPGA logic synthesis and physical synthesis products can provide full support for the new Xilinx Integrated Software Environment (ISE) 4.1i.
Logic placement speeds synthesis an extra 10%
Synplicity has enhanced its FPGA/PLD synthesis and physical synthesis software with new productivity and performance-improving features designed to enable higher quality of results.
Designers won't have to go through the hours of place and route, typical in traditional flows, to get detailed timing information.
Once the designer is happy with the results, placement from the Synplify Premier software is passed to place and route to ensure deterministic results and thus the fastest timing closure.
In addition to providing an optimal solution for timing closure, Synplify Premier 9.0 provides several algorithmic QoR enhancements and productivity boosting features such as a new user interface, additional SystemVerilog constructs and a new module generation capability.
Andy Haines, Senior Vice President of Marketing at Synplicity said: "The Synplify Premier Platform is a comprehensive environment for FPGA design comprising a variety of tools and technologies that provide improvement in analysis, DSP implementation, debug and productivity needed to successfully complete today's high-density designs".
"We worked very closely with our FPGA partners to ensure that Synplify Premier 9.0 supports the intricate architectural elements of these advanced 65nm devices".
The Synplify Premier Platform is a complete environment offering features including RTL analysis, source-level debug, HDL analysis, advanced floorplanning, physical analysis, module generators and optimisations for DSP design.
The Synplify Premier solution is also a platform for implementation and debug of ASIC and SoC prototypes using a single FPGA.
With the release of Synplify Premier 9.0, Synplicity offers additional features for improved productivity.
For example, Synplicity has expanded its SynCore IP generator to support FIFOs in addition to RAMs.
Designers supply parameters to indicate the size and type of RAM or FIFO and the IP generator wizard automatically creates technology-independent RTL ready for synthesis into an FPGA.
These features allow designers to avoid handwriting RTL or using technology-dependent memory instantiations for these functions.
Synplicity continues to extend its support for the SystemVerilog language.
New SystemVerilog features in release 9.0 include: array assignments (packed and unpacked); arrays as arguments to functions, tasks and modules; declarations in for-loop; port declarations for multiple dimensions; default argument types; and argument by names.
In order to fully address timing closure, designers must have highly accurate timing correlation between what a tool estimates and the final, actual timing.
The only proven way to get this timing correlation is to perform detailed placement and routing during logic optimisation and also to have access to FPGA-specific routing information.
Synplicity's graph-based physical synthesis is the only product on the market that performs final detailed placement of logic during optimisation and therefore, is the only tool that successfully addresses timing closure.
Actual testing on customer designs has shown that graph-based physical synthesis provides timing correlation within 10 % of final post-route timing on over 90% of designs, resulting in fewer design iterations, less time to completion and logical and physical optimisations on the actual critical paths of the design.
Synplicity's graph-based physical synthesis technology merges logic optimisation, placement and routing estimates into a single process which is used alongside a highly accurate interconnect timing graph to help ensure a design's critical paths use the fastest available routing resources in the target device.
Hitesh Patel, Director of Software Product Marketing at Xilinx said: "While the architecture in the Virtex-5 devices provides the industry with clear advantages for ultra-high density design, it did require close attention by Synplicity to marry these benefits with its FPGA design platform".
"The company came through with a solid solution that not only provides new productivity benefits, but also addressed our primary requirement for improved timing closure".
Synplify Premier 9.0 is enhanced with algorithmic changes supporting the sophisticated architectural and routing structures for improved performance and area utilisation, reducing device cost.
The huge capacity of 65nm devices, coupled with new architectural features, complex routing and high-capacity memory structures can achieve even greater quality of results through the use of specialised synthesis tools with customised algorithms.
Synplicity's physical synthesis software features a direct-mapping technology employing a variety of new heuristics tailored to minimise the number of logic elements used while still meeting timing objectives.
As ASIC designers increasingly depend upon FPGAs to prototype all or part of their designs, there is a need for a synthesis and verification environment that can take HDL code written for an ASIC and efficiently implement it in an FPGA.
The Synplify Premier platform accommodates this by performing automated gated-clock conversion handling of generated clocks and Synopsys DesignWare components.
Synplify Premier software addresses single FPGA prototypes, while Synplicity's Certify RTL prototyping product enables multiple FPGA prototypes with advanced partitioning and pin multiplexing technology.
Synplify Premier 9.0 is now available.
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