Product category:
Design and Development Software
News Release from: Synplicity | Subject: Synplify DSP 3.6
Edited by the Electronicstalk Editorial
Team on 02 April 2008
DSP tool eases complex multimedia design
Synplify DSP 3.6 includes new enhancements to architectural optimisations and DSP synthesis methodology, as well as new IP blocks and capacity improvements.
Synplicity has released a new version of its Synplify DSP ESL synthesis software for ASIC and FPGA design Synplify DSP 3.6 includes new enhancements to architectural optimisations and DSP synthesis methodology, as well as new intellectual property (IP) blocks and capacity improvements that will benefit customers working on complex digital multimedia and wireless IC designs
This article was originally published on Electronicstalk on 8 Jun 2001 at 8.00am (UK)
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The Synplify DSP tool provides a unique ESL synthesis methodology that realises significant productivity and portability advantages over traditional HDL design flows.
System and algorithm designers quickly can capture complex algorithmic behaviour using the Synplify DSP library which includes powerful modelling features such as vector arithmetic, fixed-point precision up to 128bit, and a rich set of IP cores.
The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed-optimised RTL implementations from a single model.
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Synplicity has enhanced its FPGA/PLD synthesis and physical synthesis software with new productivity and performance-improving features designed to enable higher quality of results.
This eliminates the burden of hand coding functions and architectural optimisations, achieves significantly faster design capture, speeds time to market and enables rapid design exploration that results in improved quality and lower cost.
Synplicity has enhanced the optimisation engine to recognise repeating patterns of operations in the design, and apply time-multiplexed scheduling to reduce the implementation area.
This results in much lower area across a broader set of algorithm designs.
This technique is ideal for designers working on applications such as wireless, radar, and digital video compression which typically require patterns that are highly replicated.
"Our architectural synthesis methodology will serve the needs of designers developing systems where parallelism and multiple sample rates are the design paradigm", says Chris Eddington, Synplicity's Director of DSP Marketing.
"These include applications in wireless, radar and video compression, where multiple instances of IIR, FIR filter banks and multiple channels of any type of filter block are in use".
"Our architectural optimisations can reduce real estate by as much as 90%".
For digital multimedia and wireless applications, the Synplify DSP 3.6 software now includes Reed-Solomon encoder and decoder blocks.
These functions provide burst error correction for a variety of modern communication standards used in broadband modems, digital video broadcast, storage, and military/aerospace communications.
The Synplify DSP Reed Solomon cores are extremely flexible with a broad range of wordwidth, codeword, message size, erasure and polynomial generator support.
In addition, these cores benefit from the Synplify DSP architectural optimisation methodology where tradeoffs between low area or high speed are automatically chosen based on the target technology and user constraints.
This delivers better results than parameterised RTL cores and makes Synplify DSP IP cores very easy to use for both FPGA and ASIC technologies.
Improved saturation and rounding capabilities have also been added to the Synplify DSP 3.6 library.
The tool offers a full range of rounding options across the entire library so users gain more flexibility in controlling the precision and stability of their algorithms.
To support customers implementing multiple-FPGA designs, Synplicity has improved the capacity of the DSP synthesis optimisation engine in the Synplify DSP 3.6 software.
The tool now supports 10x larger models and design complexity - ideal for military and aerospace applications where large FPGAs or multiple FPGAs are in use.
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