FPGA software brings IP into line

Allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then implement it into a variety of FPGA devices.

System Designer is a novel device-independent intellectual property (IP) configuration and system-level assembly environment that has been added to Synplicity's Synplify Pro and Synplify Premier FPGA design implementation tools.

The System Designer capability allows users to select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices, including those from Actel, Altera, Lattice Semiconductor and Xilinx.

The new tool flow provides FPGA designers, using IP and system-level blocks, with an extremely productive path to implementing complex systems in FPGAs.

System Designer is a key component of Synplicity's ReadyIP Initiative, a programme that takes aim at simplifying the access, evaluation and use of IP for FPGA-based system designs.

The ReadyIP programme allows users to evaluate and "try-before-they-buy" IP within their designs through System Designer using Synplicity's industry-leading synthesis tools; (see related press release: Synplicity Launches ReadyIP Programme: The Industry's First Universal, Secure IP Flow For FPGA Implementation).

"FPGAs have evolved into system-implementation vehicles by virtue of the increased density, speed, dedicated resources and the time to market advantages that the latest generation of programmable devices provides", says Angela Sutton, Senior Product Marketing Manager, Synplicity.

"The System Designer capability answers customers' needs for system-level implementation tools by allowing them, for the first time, to access IP from a range of vendors, evaluate the IP in the context of their design and then easily implement the system in their choice of FPGA", Sutton adds.

The System Designer tool accepts as input IP, which complies with the SPIRIT Consortium's IP-XACT standard for describing IP, and outputs top-level RTL and a Synplify project file ready for synthesising the complete design.

Third-party IP is available to System Designer users via web browser access integrated into Synplicity's synthesis products.

Through the Synplify Pro and Synplify Premier FPGA design implementation tools, designers using the System Designer capability can browse and download IP from Synplicity partners participating in the ReadyIP programme, currently ARM, CAST, Gaisler Research, and Tensilica, and thus easily evaluate various options for their FPGA designs.

System Designer is built on the open source Eclipse, a de facto standard providing for exceptional extensibility.

Additionally, the System Designer capability allows Synplify Pro and Synplify Premier users to maintain and deploy internally developed system-level building blocks and components which have been converted to the IP-XACT format, and then re-use them across multiple designs and multiple generations of FPGA designs.

"Synplicity's System Designer is a step forward for systems designers targeting FPGAs", says Graham Budd, EVP and General Manager, Processor Division, ARM.

"Customers will be able to download an evaluation version of the ARM Cortex-M1 processor and quickly configure and connect peripheral IP and then automatically generate design descriptions ready for synthesis using Synplify Pro or Synplify Premier".

"We believe it will be a great benefit to both FPGA system designers as well as our IP users".

"We've been working closely with Synplicity over the past year as the System Designer tool was in development", says Steve Roddy, Tensilica's Vice President of Marketing and Business Development.

"We believe that System Designer will boost designer productivity, enabling FPGA designers to focus more time on system analysis and less effort on system construction".

System Designer is included, at no charge, for Synplify Pro, Synplify Premier and Certify customers on active maintenance as of April 2008.

It is available immediately.

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