DFT helps Bay Montego get it right first time

Bay Microsystems has recently made the first customer shipment of its "right first time" 10Gbit/s Montego internetworking processor, developed using SynTest's DFT tools and services.

Bay Microsystems has recently made the first customer ship of its "right first time" 10Gbit/s Montego internetworking processor, developed using SynTest's DFT tools and services.

This ultra-high performance packet-processing device was implemented using 0.18-micron semiconductor process technology and was completed in record time.

This portentous achievement resulted from an accelerated bring up time, facilitated by the DFT tools supplied by SynTest Technologies.

With the release of Montego, Bay Microsystems has created a new class of network processor that combines scalability, intelligence processing and ultra-high performance in highly integrated single chip solutions, that scale from "access to long haul".

SynTest's tools and services proved invaluable by improving testability and reducing test time, thereby enabling Bay to meet its aggressive market window for release.

Tony Chiang, Vice President of Engineering at Bay Microsystems said, "We are very happy with our choice of SynTest, as our DFT partner.

By providing exemplary DFT services, and installing their tools at our site, they enabled us to test various modules on command, drastically reducing down time and maximizing our productivity.

The compact ATPG patterns generated by SynTest's TurboScan-ATPG software allowed us to reduce time-to-market using ATE to test the structural reliability of our chip design".

Dr LT Wang, President, SynTest, said: "We would like to congratulate Bay Microsystems, Tony Chiang and his team, on their stellar achievement.

We are very honored and happy that Tony put his confidence in SynTest and that we were able to contribute to their success".

To ensure a predictable outcome and eliminate potential design flaws at the last minute, and to achieve high fault coverage, Bay Microsystems chose to use DFT methodology for a scan-based design from the very beginning.

It selected SynTest's TurboScan scan insertion and ATPG tool, and SynTest's services, as well as SynTest's Turbo BSD, for boundary scan synthesis, to facilitate the testing of it's memory BIST and full scan chains on multiple-linked modules.

Tony Chiang noted, "With the goal of minimising the drain on our internal resources, we decided to look for a partner with a complete set of proven and easy-to-use DFT tools, who could support our efforts".

"Our primary concern was to take action up front to detect errors and to avoid costly and time-consuming mistakes, down the road.

It was crucial not to get bogged down with lots of debugging after the chip had taped out.

We would lose the valuable time gained by using a modular approach.

The chip was going to be complex and huge and we knew that functional tests would not be adequate and reliable.

We had to have high fault coverage and compact ATPG patterns.

SynTest helped our stellar design team achieve our goals".

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