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Synopsys
Address:
Imperium, Imperium Way
Worton Grange
Reading
RG2 0TD
UK
Telephone: (UK) +44 118 9313822
http://www.synopsys.com
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Listing of all 359 news releases from Synopsys:
VMM methodology speeds I/O design
User application article Pairing the VMM methodology with the VCS tool enabled NextIO to efficiently build highly accurate system-level and unit-level simulation environments that quickly identify design bugs.
News from Synopsys ( 9 May 2008)
PCI Express IP moves to next generation
Industry's only complete silicon-proven PCI Express 2.0 IP solution from a single vendor includes digital controllers, PHY and verification IP.
News from Synopsys (29 April 2008)
Etching simulation eases Toshiba's research
User application article Sentaurus Process and Device uses detailed physical models for simulating the fabrication process and electrical behaviour of a wide range of semiconductor devices.
News from Synopsys (24 April 2008)
USB2.0 IP receives PHY certification
Synopsys' DesignWare USB 2.0 nanoPHY uses half the power and die area of previous USB PHY IP solutions and enables faster time to market with reduced risk.
News from Synopsys (18 April 2008)
PCI Express endpoint controller runs on FPGAs
The DesignWare LE IP for PCIe is a cost-effective solution that provides innovative ease-of-use features to simplify the complexities of transitioning to PCI Express.
News from Synopsys ( 3 April 2008)
Software avoids SoC traffic jams
The ability to predict, visualise and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place and route.
News from Synopsys ( 1 April 2008)
Synopsys to acquire Synplicity
In addition to Synplicity's leading solutions for FPGAs, Synopsys will gain a differentiated rapid prototyping portfolio that complements its virtual prototyping business.
News from Synopsys (21 March 2008)
Place and route software works down to 45nm
Qualification brings the advantages of 45nm technology to a broader community of IC designers.
News from Synopsys (19 March 2008)
Design upgrade maximises IC throughput
The combination of increasing IC complexity and shrinking semiconductor features is driving increased demand for design and manufacturing-related compute resources.
News from Synopsys (13 March 2008)
IP agreement provides memory density boost
High-density SRAM-1T memory IP enables integration of up to three times more memory than a standard 6T-SRAM, enabling chips to incorporate more system memory on-chip.
News from Synopsys ( 7 March 2008)
Hierarchical system tackles large designs
The IC Compiler 2007.12 hierarchical design flow enables a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout.
News from Synopsys ( 4 March 2008)
Design flow lowers testing costs
The reference flow uses Design Compiler Ultra topographical technology to accurately predict post layout timing, power and area during synthesis
News from Synopsys (28 February 2008)
Tool suite eases chip development
The Synopsys Eclypse Low Power Solution enables design teams to adopt advanced low power techniques while boosting productivity and reducing risk.
News from Synopsys (26 February 2008)
Test generator isolates small delay defects
User application article Higher test quality enables defective parts to be identified earlier in the test process, lowering the cost of production testing.
News from Synopsys (15 February 2008)
Wireless chipsets are verified faster
User application article The VCS functional verification solution has enabled Radiospire to architect an advanced constrained-random, coverage driven environment to extensively verify the AirHook designs.
News from Synopsys (15 February 2008)
Scan compression eases HDTV IC test regime
User application article DFT MAX automatically implements scan compression on-chip, which can reduce the amount of data required to test each manufactured part by 95% or more.
News from Synopsys (13 February 2008)
Sleep state cuts USB power consumption
The DesignWare USB LPM IP digital controller and PHY IP implement a new power sleep state to reduce power consumption.
News from Synopsys ( 5 February 2008)
IP integration provides bandwidth for digital TV
The integration of the DesignWare DDR Protocol Controller IP and the Arteris NoC solution provide designers with memory traffic bandwidth and quality of service.
News from Synopsys (31 January 2008)
Simulation software aids optoelectronics design
Software links with new hardware to enable up to 20 times faster electromagnetic simulation of optoelectronic devices such as CMOS image sensors.
News from Synopsys (28 January 2008)
Software slashes nanometre design times
The 2007.12 release Synopsys' PrimeTime suite has managed an average 2X runtime improvement and 33% memory reduction over the 2006.12 release.
News from Synopsys (24 January 2008)
EDA tools standardise on Unified Power Format
STARC adopts statistical timing signoff tool
Circuit simulator slashes IC analysis cycles
Parasitic extraction works on 45nm process
Wireless USB Device IP passes the test
Reference design flow eases chip evaluation
IC test generator takes power criteria onboard
Test module suits design companies
Verification systems handle complex SoCs
Acquisition harnesses mixed-signal verification
Simulator speeds standard cell signoff
Environment enables IC design in UAE
US systems receive new certification
Library suits virtual platform assembly
HPC solution cuts MDP turnaround
Design system chosen for GPS ICs
Technology improves testing accuracy
Acquisition to expand IP portfolio to DDR
Development platform precedes Marvell processor
Acquisition addresses power management challenges
Measurement link aids optical proximity correction
Design platforms go with TSMC's flow
PCB design and simulation go hand in hand
Topographical technology speeds cameras to market
65nm process PHY meets USB specs
Topographical technology aids ASIC layout
DesignWare IP for AMBA 2 and AMBA 3 AXI protocols
USB host and dual-role device work without wires
EDA tool interoperability in focus
Design synthesis takes topographical route
Collaboration on e-beam pattern inspection tools
Place and route software supports 45nm process
Mixed-signal simulator aids charger design
DesignWare Verification now in consortium toolset
Library characterisation software released
Updates released for library compiler
Analogue and mixed signal verification for SOCs
Software verifies low-power features in new chips
Timing and noise models work with Galaxy platform
Synopsys and Magma bury the hatchet
ISQED recognition for Chan and Keating
Design software reduces turnaround time
High-definition decoder built with synthesis tools
Diagnostics accelerate yield learning
Device paramater measurement added to Hercules PVS
Serdes wins product of the year award
ASIC company standardises on timing tools
Timing and noise models for nanometre processes
Compression cuts costs of nanometre testing
Three additional cards for VMM tester
OPC software optimised for Intel Core servers
Semiconductor design specialist Q1 revenues up 15%
PCI Express IP works with NXP PHY
PCI Express IP passes latest specs
Design Compiler boosts ASIC development
Mplicity uses Formality for equivalence checking
Williams honoured for lifetime achievement
Proposal enhances IEEE1481 SPEF standard
IP programme provides access to PowerPC cores
Contribution aids SystemC-based virtual platforms
Compression software expands Oki's test coverage
HVMOS device model verifies display driver ICs
Place-and-route software to minimise design risks
Functional verification speeds SuperHyway bus SoCs
Topographical technology in new 65nm methodology
Cypress deploys Synopsys PrimeRail
Compression reduces Sanyo's test data by 90%
In-house supercomputer is one of the best
Wolfson signs for design, verification and IP
Freescale signs for verification support
New-generation compiler takes half the time
IP puts PCI Express on Amba-based SoCs
Links accelerate IC yield ramp
Test reference flow checks on-chip memory
Korean chip designers get it right first time
Harness software links with UGS PLM
Test pattern generator targets delay defects
DFM software addresses 45nm challenges
Design planner improves power implementation
Standard cells support signoff analysis tool
Testbench doubles verification productivity
Synthesis tool accelerates microdisplay design
Automatic test pattern generator accelerated
Development platform puts PCI Express IP on trial
Alliance targets lithography below 45nm
Simulator characterises standard cell library
Mask technology boosts SRAM yields
Donation opens access to power management
Verification IP covers OCP-based SoCs
Mixed-signal IP moves to 130nm process
Compiler aids SoC differentiation
Topographical technology shortens time to market
Acquisition marries design and manufacturing
Library expands for sub-65nm coverage
Assertion checkers donated to Accellera
E-Tools takes interoperability award
Fast turn-around time on Intel Dual-Core Xeon 5160
Synopsys primeyield LCC links to IC compiler
Statistical capabilities for primetime
Scan compression automation proves popular
Verification methodology proves popular
Platforms support 65nm reference flow
Extended RTL-to-GDSII low-power reference design
Faster to market using Galaxy design platform
Advisory board kicks off Liberty standard at DAC
Library reduces delay in IC designs
IBM and Chartered team with Synopsys
Verification suite speeds video kit to market
Extended physical synthesis speeds IC to market
Timing and signal integrity analysis come together
USB 2.0 IP runs on TSMC's 90nm LP process
Synopsys continues IC Compiler momentum
HDTV chip with Synopsys' IC Compiler taped out
Vietnamese designers adopt EDA tools
TCAD tools run on dual-core processors
Certified Wireless USB IP to star at forum
Bridge IP links on- and off-chip interconnects
Design for manufacturing tools join TSMC portfolio
Library lends IP support to 65nm process
Tools smooth the way from FPGAs to 65nm process
Board to evolve open-source modelling
Reference methodology covers latest ARM processor
Forum focuses on EDA tool interoperability
Irish consultants support methodology manual
PHY cores cut design work on Flash management SoCs
IP puts mobile storage host controller on chip
Simulator supports VHDL-AMS modelling
Topographical technology cuts time to market
Agere standardises digital design flows
Writing testbenches using SystemVerilog
Design for test saves wireless IC costs
Sony adopts design for manufacturing
Chinese designers adopt Galaxy
Synthesis software cuts test costs of graphics ICs
Place-and-route software speeds production flow
Sequans standardises on RTL verification
Cypress commits to design platform
Platforms support multithreaded SPARC designs
SystemVerilog support covers full design chain
Verification IP supports SystemVerilog development
ATI adds parasitic extraction tool
IBM recognises pioneering work in SoC project
Reference design flow is enhanced for 90nm
In-house design environment goes to market
Place-and-route system helps ST tape out at 65nm
IEC award for testbench automation tool
Interface IP eases USB 2.0 integration
Japanese companies add support for SystemVerilog
PCI Express controller IP supports latest specs
NEC adopts phase-shift mask technology
Migration service smoothes way to SystemVerilog
Software helps designers perform power analysis
Galaxy Design Platform supports CCS modelling
Calibration library adds ion implantation data
Design flow speeds switch to 90nm process
GDSII and MEBES compression integrated with CATS
Adaptive scan technology reduces tester costs
Simulator helps Exar speed up chip development
Diagnostic tools boost IC yields
Verification platform proves complex switch chips
RTL verification solution simplifies switch tests
TCAD tools help explore new concepts
Marvell goes from RTL to GDSII
IC floorplans take account of package constraints
Wireless USB demo meets certified specs
ASIC designer accelerates chip development
Reference flow speeds Chinese IC design
Design tools support OASIS file format
Platform helps meet wireless SoC yield goals
RTL verification speeds TV processor to market
Design platform cuts power for STARC
Award acknowledges EDA interoperability efforts
Models help depict first-order nanometre effects
Big names collaborate on mobile EDA
Acquisition to add technology CAD expertise
Microchip optimises complex analogue designs
FPGA software extends to latest Xilinx devices
Simulator speeds analogue-RF circuit verification
NEC takes on optical proximity correction
Programme aims for photomask improvements
Samsung signs up for intellectual property
USB cores extend down to TSMC 90nm process
Core is first to meet PCI Express specs
SMIC adopts optical proximity correction
PHY IP completes PCI Express solution
Renesas standardises on signoff solution
Open-source language aids mixed-technology design
Collaboration aims for systems-level SoC design
IP-based flow accelerates SoC design
Reference flow takes design platform onboard
Software addresses core power issues
Circuit simulation boosted twenty-fold
Renesas plans to improve turnaround time
National Semiconductor standardises on tools
Testbench technology aids RTL verification
Design and verification for new 90nm process
Upgrade for silicon-versus-layout verification
Toshiba tapes out multiple 90nm SoC designs
Platform delivers 222-million-transistor GPU
Collaboration cuts ARM core based design cycles
New approach integrates IC design and manufacture
Deep submicron designs stand the test of time
Reference flow supports top-performing core
Parasitic extraction package validated
Synopsys adds EDA voice to standards organisation
USB solution bundles IP with driver software
Phase-shift technology aids Motorola SOI shrink
Office shows long-term commitment to China
FPGA synthesis answers prototyping challenge
Parasitic extraction solution verified for TSMC
Honeywell signs for help with rad-hard ASICs
Synopsys back on the acquisition trail
Optical proximity correction software runs faster
Timing analyser speeds through large SoC designs
Toshiba takes PSM route to 65nm
ATI Technologies makes long-term commitment
Acquisition adds to analogue abilities
Testbench automation tool speeds verification
Learn all about SystemVerilog for free
Process simulator reaches atomic levels
Tools to run faster on 64bit platforms
Reference design flow aids MeP development
Programming interface promotes tool integration
Tools run faster on latest 64bit systems
More than 30 companies support SystemVerilog
Support for Advanced Switching Interconnect
Consulting service to help SoC designers
Verification platform gains mixed-signal simulator
ARM design software takes signal integrity onboard
Deterministic logic BIST cuts SoC test costs
Libraries and tools qualified for 90nm process
Pair to promote PCI Express interoperability
Platform to demonstrate PCI Express compatibility
Design platform speeds network processor tape out
Multitechnology simulation cuts prototype costs
Renesas improves its design closure time by 30%
Bluetooth IP is optimised for single-chip radio
Synopsys acquires InnoLogic Systems
Software to optimise Motorola CDMA2000 designs
Design flow aids frugal power design
Tools form basis of TSMC Reference Flow
Design platform takes on signal integrity tool
Toshiba signs off at 90nm with Star-RCXT
Analyser speeds to faster timing signoff
Reference methodology speeds the ARM design race
Synopsys completes Numerical acquisition
Test solution aids core-based design development
Group works towards EDA interoperability
Design database is up for grabs
Complete platform covers advanced IC design
Synopsys acquires lithography-enabling solutions
Design reference flow to speed IBM foundry
Astro speeds design closure for Sonet/SDH framer
Verification focuses on telecomms SoCs
Grantmaker award is recognition for philanthropy
Tensilica standardises on Physical Compiler
SI tools qualified for new TSMC reference flow
Open software advances EDA interoperability
SystemC modelling for OCP-based SoC design
Library gains noise modelling data
Logic BIST reduces SoC test data and time
Design methodologies speed time to ARC silicon
Addon speeds automatic test pattern generation
Core cuts cost and complexity of Bluetooth SoCs
Design rule checker runs down to 90nm
Vera speeds verification of Sonet/SDH chip
Synopsys to acquire Co-Design Automation
Physical synthesis tool runs twice as fast
Synopsys to boost IP with inSilicon acquisition
Bricaud takes over IP at Synopsys
IP library gains memory resources
Circuit simulator joins Cadence environment
Service firms up on soft IP cores
Synopsys puts its weight behind Accellera
Award recognises EDA interoperability efforts
Compiler reduces floorplanning iterations
Observed coverage boosts smart SoC verification
TI adds delay calculation to its Pyramid
SoC integration methodology speeds ARM trade
RTL performance prototyping characterises soft IP
Faster-running RTL synthesis solution
Mixed language checking package aids design reuse
STMicroelectronics endorses Synopsys simulator
TI recognises Synopsys with supplier award
Synthesis speeds Fujitsu ASIC sign-off
Hardware verification takes on new Intel spec
Physical synthesis extends beyond 20 million gates
Simulator supports latest standardised Verilog
Formal verification solution cuts setup and debug
Cafe serves up menu of design tools
Synopsys and STMicroelectronics to cut test costs
More flexibility for FPGA design software
Crosstalk analysis extended to standard cells
TAEC takes Physical Compiler for handoff
Triple the performance from latest simulators
Libraries qualified for analysis
Synopsys helps Corrent to market with complex SoCs
Simulator spans from concept to implementation
Physical Compiler reduces SGI's time to market
Easier route to SoC memory characterisation
New modelling technologies benefit big SoC designs
Altera and Synopsis to simplify SoPC design
Synopsys helps with the MIPS power budget
Synopsys acquires technology from C Level Design
Upgrade boosts verification performance
Library gains high-speed USB transceiver
Improved compiler speeds SoC design
IBM takes in Synopsys design planner
Physical design planner aids telecomms ASIC design
Cores for celebration at growing IP library
Synopsis design centres join ARM design programme
Programme aids IP and verification for OpenVera
Verilog simulator gains verification capabilities
The art of verification with VERA
Synthesis tools speed set-top-box chip design
Synopsis is so predictable for AMCC
Synopsis expands design flow solutions
Synthesis solution supports latest FPGAs
TSMC to support TetraMAX test pattern generation
Power Compiler adds pushbutton power optimisation
TI adopts Scirocco for its RTL regression farm
Hanford of Synopsis wins Women in EDA Award
PCI core gets official seal of approval
Synopsis adds crosstalk analysis to timing tool
UMC, Synopsys and Virtual Silicon collaborate
