Power Compiler adds pushbutton power optimisation

Oki Semiconductor has added Power Compiler, Synopsys' pushbutton power optimisation tool for RTL and gate-level designs, to the set of Synopsys tools offered in Oki's advanced ASIC design kit.

Oki Semiconductor has added Power Compiler, Synopsys' pushbutton power optimisation tool for RTL and gate-level designs, to the comprehensive set of Synopsys tools offered in Oki's advanced ASIC design kit.

Market demands for high-performance, high-density chip designs - such as those used in compact communications and consumer devices - are driving the need for low-power design solutions.

In addition, with the introduction of deeper sub-micron technologies, power has come to the forefront of problems faced by the mainstream ASIC designer.

Tightly integrated within the Synopsys synthesis flow, Power Compiler seamlessly fits into the current ASIC design methodology.

"Power Compiler offers unique power optimisation capabilities that will enable Oki's ASIC design community to develop power-efficient ICs for industry-leading consumer, communication and other high-performance products", said Jamshed Qamar, vice president, engineering, Oki Semiconductor.

"Given the current trends, as well as the need for low power, Synopsys' power optimisation tools form an integral part of Oki's low power ASIC design solution for 0.16- and 0.25-micron technologies".

Power Compiler, the tool of choice for power optimisation among many key ASIC vendors, enables designers of deep submicron chips (less than 0.18 micron) to automatically achieve power savings of up to 60%.

Power Compiler uses several methods to help reduce power dissipation, including RTL clock gating, operand isolation, and gate-level techniques.

It integrates seamlessly with Synopsys' Physical Compiler.

"Our customers have made it clear that low-power design solutions are critical for the success of their future designs", said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Group.

"With Power Compiler, Synopsys is uniquely positioned to address the market need for low power design by offering the only automatic power optimisation solution fully integrated in the ASIC synthesis flow.

Power Compiler has enabled many power-efficient designs and it enjoys today a high rate of adoption by users and key ASIC vendors such as Oki".

Power Compiler is available today and is priced starting at $43,200 for a one-year technology subscription license.

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