TI adopts Scirocco for its RTL regression farm

Texas Instruments has selected Synopsys' Scirocco VHDL simulator as a key component of the verification suite for its high-performance DSP designs.

Texas Instruments has selected Synopsys' Scirocco VHDL simulator as a key component of the verification suite for its high-performance DSP designs.

"Scirocco is used on our leading-edge designs, and is a part of our standard RTL regression tools within TI DSP", said Mike Fazeli, worldwide EDA manager for DSP Based Designs at TI.

"Scirocco combines superior performance and ease of use, which has improved the verification of our designs and helped us realize our demanding time-to-market goals".

Over the past year, TI has been using Scirocco as part of its verification environment, to verify their latest generation DSP designs.

Scirocco combines the flexibility of event simulation with the speed and capacity of cycle-based algorithms to deliver the fastest VHDL simulation on the market.

Scirocco's industry leading performance has allowed TI verification engineers to run more regression tests on their simulation server farm and gain significantly improved productivity.

"With the increasing size and complexity of ICs, our customers have been aggressively adopting VCS for Verilog simulation farms to dramatically improve simulation throughput", said Manoj Gandhi, general manager and sr.

vice president of the Verification Technology Group at Synopsys.

"We are excited to see a similar trend with Scirocco and are thrilled that Texas Instruments is able to take advantage of Scirocco's performance for their VHDL RTL regression farm".

Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL, and mixed-signal for complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time.

These solutions include Synopsys' VCST Verilog simulator, Scirocco VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA testbench automation tool, CoverMeter Verilog code coverage analysis tool, DesignWare verification IP, LEDA programmable HDL checker, NanoSim circuit simulation, and Formality equivalence checker.

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