Synopsis expands design flow solutions

Synopsys has completed its RTL-to-GDSII flow by introducing two high-performance tools built into Physical Compiler: Route Compiler and ClockTree Compiler.

Synopsys has completed its RTL-to-GDSII flow by introducing two high-performance tools built into Physical Compiler: Route Compiler, a standard cell router, and ClockTree Compiler, a clock tree synthesis tool.

The company has also disclosed a comprehensive signal integrity closure solution that provides prevention, analysis and repair throughout the implementation flow.

Signal integrity has become a major challenge for designers using advanced silicon processes.

Synopsys' Physical Synthesis solution provides prevention, analysis and repair of signal integrity problems throughout the design flow.

A crosstalk analysis engine, which shares common technology with PrimeTime SI, has been added to Physical Compiler.

The crosstalk analysis engine uses built-in 2.5D extraction for calculating coupling capacitance.

Signal integrity has been added to the synthesis cost function to address crosstalk problems throughout the flow.

Prevention and repair features include crosstalk-driven placement, net isolation techniques, buffer insertion, driver sizing and variable width and spacing.

Route Compiler provides designers with best-in-class timing and signal integrity- driven standard cell routing.

Unlike existing approaches that have an inaccurate view of local congestion, Route Compiler uses an innovative global routing engine to minimise hot spots caused by short nets.

This engine has a unique constraint-driven algorithm that does detail routing for short nets during global routing.

This produces designs with reduced via counts and shorter wire lengths, resulting in better manufacturing yield.

Route Compiler works on multiple processors to provide high capacity and performance for multi-million-gate designs.

Synopsys' ClockTree Compiler is built into Physical Compiler.

In addition to the simplification of the user flow, ClockTree Compiler offers significant improvements in quality of results, as compared to existing clock tree tools.

It offers 5 to 20 percent improvement in insertion delay and 5 to 10 percent improvement in clock skew.

These results are enabled by two significant technology innovations.

First, unlike other tools that are based on technologies that optimise clock trees one branch at a time, ClockTree Compiler optimises the complete tree.

This results in the best possible clock skew without sacrificing insertion delay.

Secondly, ClockTree Compiler optimises not only skew and insertion delay like other solutions, but it additionally preserves critical-path timing.

This simultaneous optimisation is enabled because ClockTree Compiler is built into Physical Compiler and uses a novel incremental placement technology.

This technology allows the clock buffers to be placed at the optimum location without causing significant perturbations to existing placement.

Route Compiler and ClockTree Compiler are available as add-on options to Physical Compiler and are currently in controlled availability.

Pricing for a single-CPU configuration of Route Compiler begins at $117,500 for a one-year time-based subscription license (TSL).

ClockTree Compiler begins at $35,250 for a one-year TSL.

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