Verilog simulator gains verification capabilities

VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis.

VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis.

The new release contains built-in comprehensive coverage analysis, enabling design teams using VCS to determine their verification quality before tapeout.

In addition, Synopsys has added VCS DirectC, a new interface to accommodate the use of C/C++ models within a Verilog verification environment.

Coverage metrics are an industry-accepted measure of simulation effectiveness.

As a standard part of VCS, designers will now have access to comprehensive built-in coverage analysis, including condition, toggle, line and finite-state-machine coverage.

Using these capabilities built into the VCS engine, design teams can easily determine the quality or "coverage" of their verification tests.

With the latest VCS release, designers only need to compile once to run both simulation and coverage analysis.

As a result of this single compilation, users will see substantially better compile and run-time performance than with previous point tool solutions that use the Verilog programming language interface (PLI).

The VCS DirectC interface significantly improves ease of use and performance over existing PLI-based methods by enabling designers to directly embed C/C++ functions within their Verilog design description.

VCS automatically recognises these C/C++ function calls and integrates them into the simulation run, in contrast to interfacing with them via manually created PLI files.

Furthermore, using this interface eliminates debugging often associated with PLIs.

As a result, VCS DirectC users can expect up to 2x simulation performance improvement over PLI.

VCS is part of Synopsys' complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL and mixed-signal simulation for complex SoC designs.

These solutions, aimed at achieving the highest verification productivity, include Synopsys' VCS Verilog simulator, Scirocco VHDL simulator, the MX package for mixed-HDL simulation, CoCentric System Studio for SystemC simulation, VERA testbench automation tool, VCS-NanoSim package for mixed-signal simulation, and Formality equivalence checker.

VCS 6.0.1 with built-in coverage and DirectC will be available in October 2001.

VCS pricing begins at $20,250 for a one-year technology subscription license.

A single license enables VCS to run on any supported platform.

Back to top