Product category:
Design and Development Software
News Release from: Synopsys | Subject: NEC Electronics (Europe)
Edited by the Electronicstalk Editorial
Team on 10 October 2001
Physical design planner aids telecomms
ASIC design
NEC Electronics (Europe) has successfully used Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622MHz telecommunications ASIC chip.
NEC Electronics (Europe) has successfully used Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622MHz telecommunications ASIC chip, using NEC's 0.18-micron process with ball grid array packaging By adopting Chip Architect in its flow, NEC was able to substantially reduce design time by several weeks
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Following this successful engagement, NEC has integrated Chip Architect into its standard design kit for 0.18-micron and below SoCs.
Faced with the challenge of implementing a complex, multimillion-gate chip for a European telecommunications customer, NEC turned to Synopsys' Physical Synthesis for the solution.
NEC designers, in collaboration with their customer, used Chip Architect for design planning, partitioning and analysis, before performing optimisation for timing closure with Physical Compiler.
"Chip Architect allowed us to create a floorplan that successfully incorporated all the key NEC-specific physical design constraints, power plan and macro placements requirements, and it allowed us to do timing and routability analysis at an early stage before we committed to block level implementation", says Thomas Langfermann, manager of European Design Centres for NEC Electronics Europe.
"Initially, our design flow did not include Physical Compiler, but we ended up using it to help us with timing closure problems.
Chip Architect saved us several weeks on the schedule.
We plan to use both tools for future complex digital designs".
"NEC is clearly a leader in high performance ASICs.
We are extremely pleased that Physical Synthesis has become a standard part of NEC's design flow", said Sanjiv Kaul, senior vice president and general manager for Synopsys Physical Synthesis business unit.
"It is indicative of the momentum Synopsys' Physical Synthesis enjoys, propelled by successes such as this leading edge ASIC design".
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