Product category:
Design and Development Software
News Release from: Synopsys | Subject: DFT Compiler and TetraMAX
Edited by the Electronicstalk Editorial
Team on 31 October 2001
Improved compiler speeds SoC design
Synopsys has added new technology and capabilities to its design-for-test (DFT) and automatic test pattern generation (ATPG) products.
Synopsys has added new technology and capabilities to its design-for-test (DFT) and automatic test pattern generation (ATPG) products The ability for designers to successfully implement test for multi-million-gate SoC devices is strengthened by new capabilities in Synopsys' DFT Compiler
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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In addition, Synopsys' new TetraMAX ATPG delay test option now provides comprehensive capabilities to help designers detect timing-related defects during manufacturing test, in order to meet strict corporate quality mandates.
With the size and complexity of today's advanced ASICs and SoCs, designers' ability to efficiently implement test in these devices is a critical productivity challenge.
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DFT Compiler's new test modelling technology now supports advanced hierarchical DFT flows in Synopsys' physical synthesis environment.
The new modelling technology increases the tool's capacity by more than 3X, while increasing its speed by 7X with no impact on the product's ability to implement timing- and layout-optimised DFT.
This improvement in the capacity and performance of the industry's most widely adopted test synthesis tool will help designers keep pace with design growth and complexity.
Up to half of manufacturing defects in today's designs are timing related and may not be caught without specifically targeting delay defects.
TetraMAX DelayTest offers a structured, scan-based approach to delay testing, predictable and measurable delay test coverage, and ensures compatibility with low-cost automatic test equipment.
TetraMAX DelayTest lets designers easily create test patterns to target the most common timing-related defect models-transition delay faults and path delay faults.
Moreover, TetraMAX DelayTest integration with Synopsys' PrimeTime, the industry's leading static timing analysis tool, further enhances the tool flow and interoperability.
"Achieving fully testable semiconductor devices today requires that DFT products stay ahead of the design complexity curve", said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Business Unit.
"We have extended our award-winning TetraMAX tool to keep pace with increasing ATPG requirements.
In addition, we have made breakthroughs with the effective use of advanced test modelling technology in DFT Compiler that we believe will become a foundation of DFT for complex multi-million gate SoCs.
This new test modelling technology is based on the proposed IEEE P1450.6 Core Test Language (CTL) standard, underscoring Synopsys' commitment to build DFT tools on open standards, while continuing to deliver unique capabilities that enable our customers to achieve DFT closure".
The new capability in DFT Compiler begins shipping in December 2001.
Current DFT Compiler customers will receive this capability at no additional charge as a maintenance update.
Pricing for DFT Compiler begins at $22,500 US list for a one-year technology subscription license (TSL).
The DelayTest option to TetraMAX ATPG is currently available.
Pricing begins at $36,660 US list for a one-year TSL.
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