Upgrade boosts verification performance

Synopsys has integrated its Vera and VCS tools to boost verification performance.

Vera 5.0 from Synopsys is tightly integrated with the VCS Verilog simulator to provide faster combined run-time performance, real-time access to built-in VCS coverage metrics, and a unified graphical environment for waveform analysis.

Along with these performance and productivity enhancing features, this new release of Vera also implements a profiler to help design engineers identify performance bottlenecks and implement higher-speed testbenches.

Overall simulation performance is now improved through a number of optimisations including linking Vera directly to VCS using the VCS Direct Kernel Interface (DKI) instead of traditional slow approaches that deploy the Verilog Programming Language Interface (PLI).

Simulations with Vera 5.0 and VCS 6.0.1 now run up to 2X faster compared to previous releases of these tools.

VCS DKI is a uniquely optimised direct interface to the VCS simulation kernel that speeds up overall simulation by reducing PLI overhead and enabling VCS simulation optimisations to be applied to the design.

In addition to significantly speeding total simulation performance, VERA 5.0 greatly enhances the quality of the overall verification environment by providing real-time access to built-in VCS coverage metrics.

This built-in comprehensive capability includes line, toggle and conditional coverage integrated into the high-speed simulation engine.

Additionally, VCS' automatic extraction of state machines for state and transition coverage eliminates the need for Vera users to manually define coverage objects.

These coverage metrics, coupled with the functional coverage data available in Vera, allow designers to direct their verification efforts to the untested areas of the design, thus eliminating testbench redundancy and improving overall efficiency of the verification environment.

Vera 5.0 offers a new performance profiler that enables design engineers to view the impact of testbench design decisions on simulation performance.

The profiler highlights the tasks taking the most simulation time, allowing designers to identify testbench bottlenecks and optimise them to improve overall performance.

"Our customers are demanding higher performance and greater integration between our products to keep up with verification of increasingly large designs", said Farhad Hayat, vice president of marketing for the Verification Technology Group at Synopsys.

"The unique integration of Vera 5.0 and the latest VCS release significantly empower faster and smarter functional verification".

Synopsys provides a complete line of integrated functional verification solutions, aimed at achieving the highest functional coverage in the shortest amount of time for complex IC designs.

These solutions include Synopsys' VCS Verilog simulator, Scirocco VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, Vera testbench automation tool, DesignWare verification IP, LEDA programmable HDL checker, NanoSim circuit simulation and Formality equivalence checker.

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