Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 15 November 2001
Synopsys acquires technology from C
Level Design
Synopsys has entered into an agreement to acquire technology assets from C Level Design.
Synopsys has entered into an agreement to acquire technology assets from C Level Design Synopsys plans to integrate C Level Design's CycleC simulation technology into Synopsys' VCS simulator to accelerate HDL simulation
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Synopsys has also agreed to acquire the technology behind C Level's System Compiler software for RTL-C synthesis, as well as the Panchul patent for synthesising high-level languages into HDL.
The purchase price for these technologies was not disclosed.
The transaction does not include any products, service businesses, customer agreements or other assets and liabilities of C Level Design.
C Level Design will discontinue sale and support of all products and services.
The CycleC simulation technology will complement the recently announced DirectC interface within Synopsys VCS, providing customers with faster cycle-accurate simulation performance when using a mixture of Verilog and C++ languages.
"VCS has a strong track record of performance improvements in Verilog simulation'', said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys.
"The addition of the CycleC technology will benefit customers by making it easier to accelerate their VCS simulations using cycle-accurate C and C++".
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