Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 16 November 2001
Altera and Synopsis to simplify SoPC
design
Altera and Synopsys are to create ASIC-like design solutions for system-on-programmable-chip devices to meet the need for next-generation design and verification flows for high-density PLDs.
Altera and Synopsys are to jointly create ASIC-like design solutions for system-on-programmable-chip (SoPC) devices to meet the need for next-generation design and verification flows for high-density programmable logic devices (PLDs) Designers will benefit from the application of technology such as.lib, SDC and SDF industry standards to increase the performance and flexibility of PLD design and verification flows
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
Related stories
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
Tensilica standardises on Physical Compiler
Tensilica has standardised on Synopsys Physical Compiler and developed a high-performance reference flow around Physical Compiler for its Xtensa V processor cores.
"In response to the evolving complexity of SOPC solutions, Altera is working to provide customers with a more comprehensive design environment to maximise the power and performance of our programmable logic devices", said Erik Cleage, senior vice president of marketing at Altera.
"This partnership with an industry-leader such as Synopsys confirms our commitment to provide our customers with best of breed technology, products, and services".
"We see our mutual customers targeting increasingly complex applications in Altera SoPC solutions", said Sanjiv Kaul, senior vice president and general manager of the physical synthesis business unit at Synopsys.
Further reading
PCI core gets official seal of approval
In conjunction with IP 2001 Japan, Synopsys has announced the PCI Special Interest Group (PCI-SIG) certification of the DesignWare PCI-X MacroCell.
Power Compiler adds pushbutton power optimisation
Oki Semiconductor has added Power Compiler, Synopsys' pushbutton power optimisation tool for RTL and gate-level designs, to the set of Synopsys tools offered in Oki's advanced ASIC design kit.
"By leveraging our strength in ASIC design and verification, we provide our mutual customers with the power they need to take full advantage of Altera's high-performance programmable logic devices and win in the marketplace".
Synopsys and Altera are collaborating closely to develop next generation design flows.
With the use of the.lib and SDC standards, Altera and Synopsys are able to leverage ASIC techniques for bringing performance and productivity to complex, high-density PLD design.
For example, a wide variety of design constraints can be used to control the synthesis process to achieve the desired clock speed and area in a PLD.
Synopsys makes available the SDC constraint format, which allows Altera's customers to use the same constraints for PLD designs as used in high-density ASIC synthesis.
The same SDC constraints are then applied in place and route, saving time and bringing yet more control to the flow.
This arms designers with more influence over the final implementation without getting caught in recode-and-reverify loops.
Building on the.lib, SDC, and SDF standards also allows the two companies to deliver a design flow that automatically works with proven verification tools such as PrimeTime static timing analysis and VCS high-performance Verilog simulator.
These flows are certified for use in verifying designs targeting Altera's high-density PLDs.
Formality formal verification, Scirocco VHDL simulation and LEDA Checker RTL rule-checking tools will be added to the PrimeTime and VCS flow to create a time-saving alternative to debugging a large PLD.
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
