Product category:
Design and Development Software
News Release from: Synopsys | Subject: SGI
Edited by the Electronicstalk Editorial
Team on 25 January 2002
Physical Compiler reduces SGI's time to
market
SGI has successfully used the Synopsys Physical Compiler to tape out its latest chip, a scaleable hub.
SGI has successfully used the Synopsys Physical Compiler to tape out its latest chip, a scaleable hub that implements the revolutionary, high-performance SGI NUMA architecture for future generation products The scalable hub serves as a processor interface, memory controller, I/O controller and connection to the high-speed memory SGI NUMAflex technology
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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Using Physical Compiler, SGI realised a three month savings in turnaround time over its traditional flow.
SGI plans to use Physical Compiler as an integral part of its hierarchical ASIC flow to enable increased performance and reduced time-to-market for next-generation products.
"Physical Compiler played a central role in the success of our scalable hub (SHub) ASIC design comprising 13 million gates and multiple clock domains up to 800MHs.
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We estimate that this one-pass flow saved us up to three months in meeting our time-to-market goals", said Eric Fischer, physical design group manager at SGI.
"Since the tool's inception, we have worked closely with Synopsys in the development and tuning of Physical Compiler.
With the successful tapeout of SHub, we are now using Physical Compiler as an integral part of our design flow".
"Synopsys is very pleased that a server and systems leader such as SGI has been able to leverage Physical Compiler so successfully in the design of its extremely complex SHub", said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis business unit, Synopsys.
"Customer successes like this are propelling Synopsys' Physical Synthesis to become the design standard at dosens of companies around the world".
Due to the immense gate and pin count of the scalable hub ASIC, SGI developed a hierarchical design flow containing 43 blocks, with the largest block being 1.3 million gates.
Physical Compiler was used on all blocks.
SGI generated placement information and detailed routing along with the synthesised netlist and handed this off to IBM.
SGI had such high confidence in Physical Compiler's ability to resolve the design complexity issues that a module could not proceed to routing unless it first went through the flow and was found to meet timing.
The new SGI scalable hub ASIC chip contains more than 13 million gates fabricated in the IBM six-layer metal, 0.18-micron SA27E technology.
It has 18 different clock domains ranging in speed from 200 to 800MHs.
It also uses full "area array," a technology that distributes the pins, 1124 signal I/Os total, across the entire device.
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