Simulator spans from concept to implementation

Synopsys has added a commercial SystemC simulator to its latest CoCentric System Studio release.

Synopsys has added a commercial SystemC simulator to its latest CoCentric System Studio release.

System Studio now supports the joint verification and analysis of algorithms, architectures, hardware and software, accelerating the development of competitive SoCs.

System Studio vastly simplifies the system-level SoC design flow by offering one simulator that spans from concept to implementation in hardware and software.

The combination of CoCentric System Studio and CoCentric SystemC Compiler, Synopsys' SystemC synthesis product, provides the most advanced SystemC design and verification solution available today.

"Design of very complex chips is moving to the transaction level in SystemC, with RT-level detail added for synthesis once the design team has closed on the architecture", said John Chilton, senior vice president and general manager for the IP and Systems Group at Synopsys.

"With our new SystemC simulator, combined with our existing SystemC synthesis product, we provide designers with the essential tools for this new design paradigm.

With this announcement, SystemC-based design is here".

While Hardware Description Language (HDL)-based register transfer level (RTL) verification remains critical for detailed hardware design, it is not sufficient for system-level SoC design.

System Studio's SystemC simulator enables designers to verify complex SoCs with multiple processors, buses and peripherals earlier in the design cycle.

The simulator allows designers to simulate hardware and software interaction at higher levels of abstraction than traditional RTL, therefore resulting in orders-of-magnitude simulation speed-up.

Finally, System Studio's flexibility to mix different abstraction levels using a single language enables designers to optimise the design and verification flow for SoC projects.

Verifying the real-time interaction of hardware and software in the application environment is a critical step to ensure the products being designed are functioning correctly.

Unfortunately, the current hardware/software coverification approaches attack the problem too late in the design cycle.

They require a fully detailed RTL HDL description of the hardware, making the verification of embedded software inherently slow.

In addition, if major design flaws are discovered at this stage, it is usually too late to recover.

The solution is to create a system-level hardware representation that simulates quickly and can be used to run and debug embedded software early in the design cycle.

"We validated a SystemC-based design flow with Synopsys and found advantages to modeling, verification and analysis in the early design stages of SoC development", said Kasu Yamada, general manager, NEC Electronics.

"We designed and simulated MPEG components from algorithm to behavioral SystemC for the architecture tradeoff and embedded software debugging.

CoCentric System Studio helped us describe, execute and analyse the whole system easily and efficiently".

In the past, due to the lack of a standard system-level design language, design teams resorted to proprietary extensions of C and C++ for their system-level verification efforts.

As a consequence, it was difficult to use other design team's models.

CoCentric System Studio is part of Synopsys' complete line of functional verification solutions supporting SystemC, Verilog, VHDL, mixed-HDL, and mixed-signal simulation for complex SoC designs.

These solutions, aimed at achieving the highest verification productivity, include Synopsys' VCS Verilog simulator, Scirocco VHDL simulator, the MX package for mixed-HDL simulation, VERA testbench automation tool, VCS-NanoSim package for mixed-signal simulation and Formality equivalence checker.

CoCentric System Studio 2002.05 will ship in May 2002.

Pricing for CoCentric System Studio starts at US$ 26,950 for a one-year technology subscription license (TSL).

Customers with current maintenance agreements will receive the release at no additional cost.

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