Product category:
Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial
Team on 28 February 2002
TAEC takes Physical Compiler for handoff
Toshiba America Electronic Components (TAEC) has adopted Synopsys' Physical Compiler for placement-based handoff.
Toshiba America Electronic Components (TAEC) has adopted Synopsys' Physical Compiler for placement-based handoff TAEC has already deployed the placement handoff flow with Physical Compiler to successfully tape out two complex SoC designs for a strategic customer
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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TAEC in now including Physical Compiler in its design flow as well as making the tool an integral part of the design kit for its ASIC customers.
In a traditional netlist-only handoff design flow, there are typically several time- consuming iterations between the ASIC customer and ASIC vendor to achieve timing closure.
In the placement handoff flow with Physical Compiler, accurate placement-based interconnect delays are used to do unified synthesis and placement.
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The resulting placed netlist has a much faster path to post-route timing convergence, with minimal iterations.
"Toshiba is continually investing in leading-edge technologies to maintain its highly competitive edge and to meet our customers' complex design requirements.
By adopting the placement handoff model with Physical Compiler, and accepting placement information from customers, we were able to substantially reduce design iterations and quickly tape out two complex designs for a prominent customer", said Jeff Berkman, senior vice president of engineering at TAEC.
"Due to these impressive results, we decided to make Physical Compiler an integral part of both our internal and ASIC customer flows".
The TAEC customer - a maker of scaleable Ethernet devices - achieved success taping out two multi-million-gate designs using Physical Compiler in both a hierarchical and a flat design flow.
Both designs were fabricated using Toshiba's TC260 0.18-micron, six-layer metal process.
By providing placement information and a synthesized and optimized netlist to TAEC, the customer was able to significantly accelerate timing closure, when compared to the traditional flow of a netlist-only handoff.
"In the highly competitive networking arena, getting a product to market on time is key", said Takashi Yoshimori, system LSI design division general manager at Toshiba.
"By adopting placement handoff with Physical Compiler, TAEC was able to significantly reduce the overall design cycle time".
"Synopsys' Physical Compiler has become the critical technology for accelerating customer designs.
By helping partners like TAEC make Physical Compiler an integral part of their design flow, we help their customers succeed", said Sanjiv Kaul, senior vice president and general manager of Synopsys' Physical Synthesis Business Unit.
"As an ASIC leader, TAEC's endorsement of Physical Compiler is yet another prime example of the customer success that has established Synopsys' Physical Synthesis as the design standard at scores of leading companies around the world".
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