Product category:
Design and Development Software
News Release from: Synopsys | Subject: VCS 6.2
Edited by the Electronicstalk Editorial
Team on 04 April 2002
Simulator supports latest standardised
Verilog
The latest release of the Synopsys VCS Verilog simulator, VCS 6.2, now supports the Verilog-AMS language through a technology platform called VCS DirectAMS.
The latest release of the Synopsys VCS Verilog simulator, VCS 6.2, now supports the Verilog-AMS language through a technology platform called VCS DirectAMS This new platform interface enables designers to run high-capacity, high-performance mixed-signal simulation of Verilog-AMS and Spice using a combination of the VCS Verilog simulator and circuit simulators VCS 6.2 provides circuit simulator integration through DirectAMS, a user-transparent platform that enables VCS to read in designs described with Verilog, Verilog-AMS, Spice, or a combination of these formats
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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VCS DirectAMS extends Synopsys' multilevel, mixed-signal verification solution, which currently consists of VCS' Direct Kernel integration with NanoSim, an industry-proven fast Spice simulator for memory and mixed-signal designs.
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Available during the second half of 2002, NanoSim integration via the VCS DirectAMS will deliver flexibility to verify complex SoCs by enabling designers to deploy superior RTL, gate, and fast Spice-level simulation engines.
Companies that choose to integrate their analogue circuit technologies with VCS through DirectAMS can work directly with Synopsys.
The first third party company to utilise the VCS DirectAMS interface, is Antrim Design Systems with its OmniSim simulator.
OmniSim integration will be available with VCS 6.2 in May 2002.
With VCS and OmniSim working together, designers can quickly execute their block-level analysis and characterisations with a seamless interface between the digital and analogue circuit domains.
"By working closely with Synopsys, we were able to produce a simulation environment that integrates two high-performance simulators to analyse and characterise block-level designs in digital, analogue and mixed-signal applications", said Roy McGuffin, Antrim's president and CEO.
"The combined Synopsys/Antrim environment will enable engineers to design their analogue circuits and mixed-signal systems with confidence".
"Mixed-signal is a key component of Cypress' communications designs", said Paul Keswick, vice president of New Product Development and Design Services, at Cypress Semiconductor.
"We have been a user of Antrim analogue design environment and an early adopter of VCS' DirectAMS integration with Antrim.
With this integration, we can now leverage VCS' excellent performance and capacity for both digital and mixed-signal designs.
The combination of Antrim's analogue design environment and Synopsys' VCS digital simulator creates a strong Verilog-AMS solution".
Verilog-AMS, a language created by the Accellera EDA standards organisation, allows engineers to describe and simulate analogue and mixed-signal designs using a top-down design methodology, as well as the traditional bottom-up approaches.
This language provides powerful structural and behavioural modelling capabilities required by designers of communications, wireless, consumer electronics and other mixed-signal applications.
With Verilog-AMS, designers can save time and effort by maintaining one netlist, rather than breaking their designs into separate analogue and digital blocks.
"By adding DirectAMS we are extending VCS' capabilities to allow more partnerships and enhance our mixed-signal solution", said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys.
"Adding Verilog-AMS support to VCS will enable engineers to use their trusted simulator of choice during more stages of their critical design flow".
Pricing for VCS starts at $20,250 for a one-year technology subscription license.
VCS 6.2 with the DirectAMS integration platform will be available in May 2002.
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