Compiler reduces floorplanning iterations

Floorplan Compiler is a high-end hierarchical design planner that enables designers to save time and money by creating high-quality floorplans in dramatically fewer iterations.

Floorplan Compiler from Synopsys is a high-end hierarchical design planner that enables designers to save time and money by creating high quality floorplans in dramatically fewer iterations.

Building an efficient hierarchical floorplan is typically difficult and time-consuming, requiring numerous iterations.

Floorplan Compiler's virtual flat approach solves this problem by eliminating the ping-pong effect that normally occurs between chip-level and block-level floorplanning.

The result is a product that enables all critical floorplanning decisions such as partitioning, block shaping, macro placement, pin assignment, and feed-through optimisation to be made in the full context of the chip, including blockages and routing hotspots.

Floorplan Compiler is uniquely qualified to address even the most complex designs.

It has a smart cluster approach that enables capacity of more than 20 million gates through intelligent partitioning.

Timing convergence is assured because Floorplan Compiler is built on the same placement technology as Physical Compiler, the leading tool for synthesis and placement of timing-critical and congested designs.

The quality of results of Floorplan Compiler's virtual flat approach and the timing closure provided by Physical Compiler combine to address the needs of high-end designs.

"We are in the middle of taping out a timing-critical six-million-gate set top box design with Floorplan Compiler.

We've been able to converge on our partitions, pin assignments, macro placements and feedthroughs in a fraction of the time it took us on our previous design", said Maynard Hammond, ASIC principal engineer, Subscriber Networks Sector, Scientific Atlanta.

"Our very first floorplan was routable and met our timing milestone.

So far, we've shaved six to eight weeks from our tapeout schedule thanks to Floorplan Compiler".

Floorplan Compiler allows users to quickly create high-quality floorplans with fewer iterations than before.

Placing and trial routing the complete design gives Floorplan Compiler a full understanding of routing blockages and route congestion.

Buffer insertion and pin and feedthrough assignments are created based on this route.

"We do some of the largest, densest and fastest designs in the industry", said Chris Malachowsky, vice president of engineering, NVIDIA.

"Historically, convergence on a floorplan that provides for both high performance and routability has required a lengthy period of iterations through many tools.

By leveraging Floorplan Compiler's virtual flat approach, we have been able to dramatically reduce the time and effort to arrive at a floorplan, while simultaneously improving the quality of results.

Because of this, we have already adopted Floorplan Compiler on our most demanding next generation design".

Floorplan Compiler's automatic handling of channel-based and abutted designs minimises overall design time while providing flexibility in implementation style.

"STMicroelectronics has taped out more than one hundred chips using the Synopsys' Physical Synthesis flow", said Marco Montalti, design methodology group director of the Digital and Analog Semicustom division, STMicroelectronics.

"Floorplan Compiler has already begun to deliver benefits to ST's designers.

We are using Floorplan Compiler in our UD2K design platform and several of our teams are using it on live designs.

What previously took us up to several weeks to converge on a floorplan can now be accomplished in a matter of days".

All timing-related operations in Floorplan Compiler, including analysis and budgeting, use embedded PrimeTime for common timing from planning to signoff.

Timing constraints as well as logical and physical libraries are shared with the Synopsys' Physical Synthesis toolset.

Rounding out Floorplan Compiler's hierarchical implementation features are a full suite of editing and floorplan analysis capabilities, and complete power routing and power network analysis.

"During the past two years we have worked closely with most of the high performance design teams worldwide.

Synopsys has leveraged these experiences to develop a product that can address even the most complex design challenges", said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis business unit, Synopsys.

"Many of the design teams we have worked with are already experiencing the significant improvements in their design flows that Floorplan Compiler is capable of delivering.

We expect Synopsys customers to find Floorplan Compiler an ideal companion to Physical Compiler".

Floorplan Compiler is available now.

Prices start at $150,000.

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