Circuit simulator joins Cadence environment

Edited by the Electronicstalk editorial team Jul 4, 2002

The Synopsys NanoSim circuit simulator has been integrated into the Cadence Analogue Design Environment using the Cadence Open Analogue Simulation Socket (OASIS).

The Synopsys NanoSim circuit simulator has been integrated into the Cadence Analogue Design Environment using the Cadence Open Analogue Simulation Socket (OASIS).

This integration is a result of Synopsys collaboration with Motorola's Semiconductor Products Sector, completed through platinum membership in the Cadence Connections Programme.

The combined solution enables companies like Motorola to verify large analogue mixed-signal SoC designs, leveraging NanoSim's speed, capacity and accuracy directly from within the Analogue Design Environment.

"Synopsys' NanoSim and the Cadence Analogue Design Environment are critical pieces of our analogue design and verification flow", said Jim Caravella, manager of Analogue Design Kits and AMS Flows at Motorola's SPS.

"We rely on NanoSim for transistor-level full-chip verification of our complex SoCs - and we use the Analogue Artist Design Environment as the cockpit for analogue, custom and mixed-signal design validation.

Bringing the two together give our analogue designers direct access to NanoSim from within the Analogue Artist Design Environment, enabling our designers to quickly characterise and debug their analogue/custom/AMS designs within a consistent and familiar environment".

The NanoSim fast-Spice simulator delivers significant speed and capacity advantages over traditional Spice simulators with Spice-level accuracy.

The comprehensive, built-in diagnostic functions of NanoSim enable users to perform a wide range of full-chip timing, functionality and power management tasks simultaneously.

NanoSim offers a multi-level, mixed-signal verification solution through the Direct Kernel Integration with Synopsys' VCS Verilog simulator.

"Our collaboration with Motorola has resulted in an integrated solution that enables streamlined, precise analogue mixed signal verification of world-class chips", said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test business unit.

"The success of this joint project exemplifies Synopsys commitment to design partnerships that drive innovation and support our best-in-class design flow".