Product category:
Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare IP library
Edited by the Electronicstalk Editorial
Team on 12 July 2002
IP library gains memory resources
A new full line of memory intellectual property (IP) includes memory models, memory controllers and memory BIST.
A new full line of memory intellectual property (IP) includes memory models, memory controllers and memory BIST The memory solution is available to designers through a single licence and price, with no per-use fees or royalty payments, as part of the Synopsys DesignWare IP library
This article was originally published on Electronicstalk on 9 Oct 2001 at 8.00am (UK)
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"We successfully met our 150MHz system operating frequency with the DesignWare memory controller, which integrated smoothly into our design environment", said Subbu Muddappa, staff design engineer, Woodside Networks.
"The complete verification solution, including Synopsys DesignWare with simulation memory models for SDRAM and Flash, enabled us to verify our entire wireless LAN solution quickly and efficiently".
The DesignWare memory controller is a fully configurable, synthesisable memory controller for dynamic and static memories.
A single memory controller can support multiple memory types such as DDR-SDRAM, SDR-SDRAM, Mobile-SDRAM, Micron SyncFlash, SSRAM, SRAM, Flash and ROM devices.
The memory controller interfaces to the system via an AMBA AHB 2.0-compatible interface and may also interface with other buses through a simple gasket.
The number of preverified memory simulation models in the DesignWare IP library is constantly growing, with more than 10,000 models covering more than 25 memory vendors' devices available today.
The models integrate with simulators through the industry de facto standard Swift interface, which is supported by all Synopsys simulators and by all other major simulator vendors.
DesignWare Memory BIST is a fully configurable, synthesisable solution for built-in self-test of embedded SRAM and ROM memory structures.
The DesignWare memory BIST solutions increase overall product quality by ensuring fault coverage of embedded memory defects through built-in algorithmic testing.
In order to reduce test time and maximise the use of embedded test resources, tests are executed in parallel with a shared BIST controller.
Four industry-standard SRAM BIST algorithms are available and can be selected at runtime: March LR, March C-, MATS++, and a retention test using a pause-polling mechanism.
"We have consistently heard from our customers that acquiring individual pieces of memory IP is becoming cost prohibitive", said Ed Bard, director of DesignWare marketing at Synopsys.
"The Synopsys DesignWare IP library gives designers immediate access to an entire memory portfolio for a single price.
The thousands of designers who already have access to the DesignWare IP library can get the newly available memory IP by simply downloading it from the DesignWare Memory Central website".
Access to the full suite of memory IP is made available through DesignWare Memory Central - a new memory-focused website that lets designers download DesignWare memory IP and documentation.
A current DesignWare licence is required in order to download.
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