Synopsys to acquire Co-Design Automation

Synopsys has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation.

Synopsys has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation, a privately held verification company focused on improving the designer's ability to efficiently create and verify SoC designs.

The combination of Co-Design Automation technology with Synopsys' industry-proven VCST Verilog simulator will enable delivery of next-generation hardware description language (HDL) solutions.

Consideration for the merger consists of cash, notes and assumed options with an aggregate value of approximately $36 million.

Co-Design Automation is the developer of Superlog, a state-of-the-art language technology that extends the standard Verilog HDL with powerful high-level programming techniques and advanced verification and behavioural modelling capabilities that allow users to easily evolve their existing design and verification methodologies.

"Co-Design Automation assembled many of the world's leading Verilog language experts to deliver Superlog technology", stated Aart de Geus, chairman and CEO of Synopsys.

"The addition of Co-Design Automation to Synopsys comes at the very moment that SystemVerilog, the next-generation Verilog language, is coming about.

Having technology pioneers such as Phil Moorby, Peter Flake and Simon Davidmann join our team of verification experts significantly accelerates our Smart Verification strategy.

The combination of Synopsys' recent VCS 7.0 release, Superlog technology and the Accellera SystemVerilog umbrella will drive the state-of-the-art of RTL design and verification forward in very short order and decisively impact design productivity".

"Joining forces with the Synopsys team is a strong step toward furthering advanced Verilog methodologies which will address the immense verification challenge our customers are facing", said Simon Davidmann, chief executive officer of Co-Design Automation.

"Synopsys' leadership in verification, coupled with Co-Design Automation's strength in design language technology, will accelerate language evolution and thus enable new levels of design and verification productivity across the industry".

"We believe that both Intel and the industry will be better served by a higher abstraction language, and we have worked closely with Synopsys and Co-Design Automation to evolve such a verification standard", said Sunil Shenoy, director of design engineering at Intel.

"Integrating the two companies' technologies will accelerate the adoption of the high-level Verilog standard in the design engineering community".

"Our partners need to efficiently verify ARM cores within their overall SoC designs.

We need to deliver robust verification environments to those licensees, including comprehensive design and verification views.

Superlog and Smart Verification provide technologies to achieve efficient verification critical for core-based design", said Simon Segars, vice president of engineering at ARM.

"Combining these technologies is great news for us and our partners who incorporate our cores into their designs".

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