Product category:
Design and Development Software
News Release from: Synopsys | Subject: Vera
Edited by the Electronicstalk Editorial
Team on 09 September 2002
Vera speeds verification of Sonet/SDH
chip
NEC Electron Devices has successfully verified its latest Sonet/SDH framer physical layer chip with Synopsys' Vera testbench automation tool.
NEC Electron Devices has successfully verified its latest Sonet/SDH framer physical layer chip with Synopsys' Vera testbench automation tool Vera's advanced features such as its easy-to-learn, intuitive OpenVera hardware verification language, allowed NEC engineers to verify their design quickly and meet demanding schedules with a high quality, reusable verification environment
This article was originally published on Electronicstalk on 8 Aug 2001 at 8.00am (UK)
Related stories
Synthesis tools speed set-top-box chip design
By combining Module Compiler and Physical Compiler, Synopsys has helped Scientific-Atlanta to cut several months off design time while gaining complete control over the design process.
The art of verification with VERA
Verification Central and Synopsys have jointly launched a new book: 'The art of verification with VERA', by Faisal Haque, Khizar Khan and Jonathan Michelson.
"Synopsys' Vera testbench automation tool enabled us to increase our verification productivity significantly more than using Verilog", said Noboru Sato, manager of Network System LSI Development Division, System LSI Operations Unit, NEC Electron Devices.
"One of the reasons we chose Vera is its powerful ability to generate pseudorandom self-checking test cases.
The technology enabled us to quickly and easily generate complex stimulus to exhaustively verify the design and ensure design success".
Further reading
Upgrade boosts verification performance
Synopsys has integrated its Vera and VCS tools to boost verification performance.
Hardware verification takes on new Intel spec
Synopsys has released OpenVera 2.0, with new additions to OpenVera assertions based on Intel's ForSpec language.
Observed coverage boosts smart SoC verification
Synopsys reckons VCS 7.0 is the first comprehensive smart verification solution to address increasing SoC verification challenges.
The NEC uPD98413 Sonet/SDH framer incorporates four 622Mbit/s synchronous optical network/synchronous digital hierarchy channels on a single chip, making it ideal for high-end WAN applications.
Verifying the chip was complex, which necessitated the creation of a random stimulus generator.
This shortened the verification time and achieved the desired coverage.
The ability to monitor packet flow and track device coverage is another verification essential.
Vera's rich feature set, which includes constraint based random generation, automated self-checking and functional coverage, made it possible for NEC to meet these requirements.
Using Vera's constraint-based stimulus generator and concise modelling constructs shortened the time required to develop the testcases and models.
Additionally, the integration with VCST coverage metrics technology permitted the tracking of simulation coverage to monitor progress of the verification flow.
The success with the Sonet/SDH design has proven Vera as an effective testbench automation tool.
"The success achieved with Vera at NEC is made possible by the tightly integrated solution of the Synopsys Vera testbench tool and its industry-leading VCS Verilog simulator.
This solution provides NEC a high performance, constraint-driven testbench automation tool", said Swami Venkat, director of marketing of testbench and formal analysis for the Verification Technology Group at Synopsys.
"NEC's WAN designs are extremely complex and require a powerful, yet easy-to-use tool to verify them.
NEC was able to thoroughly verify their designs using the powerful capabilities built into this tool".
Vera provides full support for automatic generation of stimulus, including the ability to generate directed, random and constrained random tests.
The user can specify valid ranges for complex data types and constraints for protocols to focus on difficult corner cases.
Additionally, Vera can take user-defined production rules and automatically generate a continuous stream of legal random sequences for commands or packets.
With these capabilities, Vera can be used to generate many different combinations of legal stimulus to find design errors early in the verification cycle and raise the overall quality of the verification environment.
Vera allows NEC to streamline the verification environment while providing a highly effective verification solution.
A verification environment created using Vera, can be reused due to built-in support for object-oriented programming.
Prior to using Vera on testbench projects, NEC found that it was difficult to establish a common coding style and methodology.
With Vera, bus-functional models, transaction generators, functional coverage objects and other elements of the verification infrastructure can be easily reused in other projects and shared among different locations.
The concise nature of the OpenVera language and its support for re-entrancy has also reduced the overall size of the testbench, easing maintenance issues.
• Synopsys: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
